[llvm] r309404 - GlobalISel: map 128-bit values to an FPR by default.

[Tim Northover via llvm-commits]

Author: tnorthover
Date: Fri Jul 28 10:11:01 2017
New Revision: 309404

URL: http://llvm.org/viewvc/llvm-project?rev=309404&view=rev
Log:
GlobalISel: map 128-bit values to an FPR by default.

Eventually we may want to allow a pair of GPRs but absolutely nothing in the
entire world is ready for that yet.

Added:
    llvm/trunk/test/CodeGen/AArch64/reg-bank-128bit.mir
Modified:
    llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll

Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=309404&r1=309403&r2=309404&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Fri Jul 28 10:11:01 2017
@@ -488,7 +488,8 @@ AArch64RegisterBankInfo::getInstrMapping
 
     // As a top-level guess, vectors go in FPRs, scalars and pointers in GPRs.
     // For floating-point instructions, scalars go in FPRs.
-    if (Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc))
+    if (Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc) ||
+        Ty.getSizeInBits() > 64)
       OpRegBankIdx[Idx] = PMI_FirstFPR;
     else
       OpRegBankIdx[Idx] = PMI_FirstGPR;

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll?rev=309404&r1=309403&r2=309404&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll Fri Jul 28 10:11:01 2017
@@ -79,24 +79,6 @@ define void @odd_vector(<7 x i32>* %addr
   ret void
 }
 
-  ; RegBankSelect crashed when given invalid mappings, and AArch64's
-  ; implementation produce valid-but-nonsense mappings for G_SEQUENCE.
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to map instruction
-; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for sequence_mapping
-; FALLBACK-WITH-REPORT-OUT-LABEL: sequence_mapping:
-define void @sequence_mapping([2 x i64] %in) {
-  ret void
-}
-
-  ; Legalizer was asserting when it enountered an unexpected default action.
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to map instruction
-; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for legal_default
-; FALLBACK-WITH-REPORT-LABEL: legal_default:
-define void @legal_default([8 x i8] %in) {
-  insertvalue { [4 x i8], [8 x i8], [4 x i8] } undef, [8 x i8] %in, 1
-  ret void
-}
-
   ; AArch64 was asserting instead of returning an invalid mapping for unknown
   ; sizes.
 ; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction: ret: '  ret i128 undef' (in function: sequence_sizes)

Added: llvm/trunk/test/CodeGen/AArch64/reg-bank-128bit.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/reg-bank-128bit.mir?rev=309404&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/reg-bank-128bit.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/reg-bank-128bit.mir Fri Jul 28 10:11:01 2017
@@ -0,0 +1,21 @@
+# RUN: llc -mtriple=aarch64 -global-isel -run-pass=regbankselect -o - %s | FileCheck %s
+---
+name:            test_large_merge
+legalized:       true
+registers:
+body: |
+  bb.0.entry:
+    liveins: %x0, %x1, %x2
+
+    ; CHECK-LABEL: name: test_large_merge
+    ; CHECK: registers:
+    ; CHECK:       - { id: 0, class: gpr
+    ; CHECK:       - { id: 1, class: gpr
+    ; CHECK:       - { id: 2, class: gpr
+    ; CHECK:       - { id: 3, class: fpr
+    %0:_(s64) = COPY %x0
+    %1:_(s64) = COPY %x1
+    %2:_(p0) = COPY %x2
+    %3:_(s128) = G_MERGE_VALUES %0, %1
+    %d0 = COPY %3
+...