[PATCH] D35302: [IRCE] Recognize loops with unsigned latch conditions

[Anna Thomas via Phabricator via llvm-commits]

anna requested changes to this revision.
anna added a comment.
This revision now requires changes to proceed.

Couple of minor changes. I haven't looked at the tests yet.

Do you mind separating out the `ULT/ULE` changes from the `UGT/UGE` just for ease of reviewing? Once the first part is reviewed, the second would be pretty straightforward.



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Comment at: lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp:462
   bool IndVarIncreasing;
+  bool SignedPredicate;
 
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Pls rename this as `isSignedPredicate`.


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Comment at: lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp:846
+    SignedPredicate = Pred == ICmpInst::ICMP_SLT || Pred == ICmpInst::ICMP_SGT;
+    ICmpInst::Predicate GuardPred =
+        SignedPredicate ? CmpInst::ICMP_SLT : CmpInst::ICMP_ULT;
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Pls name this as the `PredOpCode`. I got confused with guards..


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Comment at: lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp:978
 Optional<LoopConstrainer::SubRanges>
-LoopConstrainer::calculateSubRanges() const {
+LoopConstrainer::calculateSubRanges(bool SignedPredicate) const {
   IntegerType *Ty = cast<IntegerType>(LatchTakenCount->getType());
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This to `isSignedPredicate` as well. Similarly for all other booleans.


https://reviews.llvm.org/D35302