[llvm] r309269 - Added cost of ZEROALL and ZEROUPPER instrs in btver2 cpu.

[Andrew V. Tischenko via llvm-commits]

Author: avt77
Date: Thu Jul 27 06:12:08 2017
New Revision: 309269

URL: http://llvm.org/viewvc/llvm-project?rev=309269&view=rev
Log:
Added cost of ZEROALL and ZEROUPPER instrs in btver2 cpu.
Differential Revision https://reviews.llvm.org/D35834

Modified:
    llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
    llvm/trunk/test/CodeGen/X86/avx-schedule.ll

Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=309269&r1=309268&r2=309269&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Thu Jul 27 06:12:08 2017
@@ -462,5 +462,16 @@ def WriteVSQRTYPSLd: SchedWriteRes<[JLAG
 }
 def : InstRW<[WriteVSQRTYPSLd], (instregex "VSQRTPSYm")>;
 
+def WriteJVZEROALL: SchedWriteRes<[]> {
+  let Latency = 90;
+  let NumMicroOps = 73;
+}
+def : InstRW<[WriteJVZEROALL], (instregex "VZEROALL")>;
+
+def WriteJVZEROUPPER: SchedWriteRes<[]> {
+  let Latency = 46;
+  let NumMicroOps = 37;
+}
+def : InstRW<[WriteJVZEROUPPER], (instregex "VZEROUPPER")>;
 } // SchedModel
 

Modified: llvm/trunk/test/CodeGen/X86/avx-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-schedule.ll?rev=309269&r1=309268&r2=309269&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-schedule.ll Thu Jul 27 06:12:08 2017
@@ -2850,7 +2850,7 @@ define void @test_zeroall() {
 ;
 ; BTVER2-LABEL: test_zeroall:
 ; BTVER2:       # BB#0:
-; BTVER2-NEXT:    vzeroall
+; BTVER2-NEXT:    vzeroall # sched: [90:?]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_zeroall:
@@ -2875,7 +2875,7 @@ define void @test_zeroupper() {
 ;
 ; BTVER2-LABEL: test_zeroupper:
 ; BTVER2:       # BB#0:
-; BTVER2-NEXT:    vzeroupper
+; BTVER2-NEXT:    vzeroupper # sched: [46:?]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_zeroupper: