[PATCH] D35888: Changed basic cost of Store operation on X86.

[Elena Demikhovsky via Phabricator via llvm-commits]

delena added a comment.

In https://reviews.llvm.org/D35888#822536, @ashutosh.nema wrote:

> Is store is always 2 UOps on x86, independent of the type and register(xmm/ymm) ?
>
> Thanks,
> Ashutosh


Yes, if the address has index and scale. If the address is simple, IACA shows "micro fusion".
IACA is publicly available tool that shows number of UOPS and ports per instruction for Intel processors.
https://software.intel.com/en-us/articles/intel-architecture-code-analyzer


Repository:
  rL LLVM

https://reviews.llvm.org/D35888