[PATCH] D35700: DAGCombiner: Extend reduceBuildVecToTrunc to handle non-zero offset

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon accepted this revision.
RKSimon added a comment.
This revision is now accepted and ready to land.

LGTM with one minor comment



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Comment at: lib/Target/X86/X86ISelLowering.cpp:35813
+
+  if (!SrcVT.isSimple() ||
+      is128BitLaneCrossingShuffleMask(SrcVT.getSimpleVT(), ShuffleMask))
----------------
Do we need the isSimple() test? It's handled by isShuffleMaskLegal


https://reviews.llvm.org/D35700