[PATCH] D35839: [X86] SET0 to use XMM registers where possible PR26018 PR32862

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

In https://reviews.llvm.org/D35839#820405, @delena wrote:

> There is no any diff between xmm and ymm on Intel processors, AFAIK.
>  I was wrong talking about EVEX2VEX pass, btw. It will do nothing with zmm.


So should AVX512 zmm zeroing be done with ymm instead of xmm?

> Do AMD processors support AVX-512?

No, just AVX2 with Excavator (bdver4) and Ryzen (znver1) - both have 128-bit ALUs and must 'double-pump' 256-bit instructions as separate uops and then merge them at retirement. Agner's microarchitecture.pdf has more details.


https://reviews.llvm.org/D35839