[PATCH] D34965: AMDGPU/SI: Force exports at the end for SI scheduler

[Marek Olšák via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL309027: AMDGPU/SI: Force exports at the end for SI scheduler (authored by mareko).

Changed prior to commit:
  https://reviews.llvm.org/D34965?vs=105117&id=108149#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D34965

Files:
  llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp
  llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.h


Index: llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp
@@ -1130,6 +1130,62 @@
   }
 }
 
+void SIScheduleBlockCreator::colorExports() {
+  unsigned ExportColor = NextNonReservedID++;
+  SmallVector<unsigned, 8> ExpGroup;
+
+  // Put all exports together in a block.
+  // The block will naturally end up being scheduled last,
+  // thus putting exports at the end of the schedule, which
+  // is better for performance.
+  // However we must ensure, for safety, the exports can be put
+  // together in the same block without any other instruction.
+  // This could happen, for example, when scheduling after regalloc
+  // if reloading a spilled register from memory using the same
+  // register than used in a previous export.
+  // If that happens, do not regroup the exports.
+  for (unsigned SUNum : DAG->TopDownIndex2SU) {
+    const SUnit &SU = DAG->SUnits[SUNum];
+    if (SIInstrInfo::isEXP(*SU.getInstr())) {
+      // Check the EXP can be added to the group safely,
+      // ie without needing any other instruction.
+      // The EXP is allowed to depend on other EXP
+      // (they will be in the same group).
+      for (unsigned j : ExpGroup) {
+        bool HasSubGraph;
+        std::vector<int> SubGraph;
+        // By construction (topological order), if SU and
+        // DAG->SUnits[j] are linked, DAG->SUnits[j] is neccessary
+        // in the parent graph of SU.
+#ifndef NDEBUG
+        SubGraph = DAG->GetTopo()->GetSubGraph(SU, DAG->SUnits[j],
+                                               HasSubGraph);
+        assert(!HasSubGraph);
+#endif
+        SubGraph = DAG->GetTopo()->GetSubGraph(DAG->SUnits[j], SU,
+                                               HasSubGraph);
+        if (!HasSubGraph)
+          continue; // No dependencies between each other
+
+        // SubGraph contains all the instructions required
+        // between EXP SUnits[j] and EXP SU.
+        for (unsigned k : SubGraph) {
+          if (!SIInstrInfo::isEXP(*DAG->SUnits[k].getInstr()))
+            // Other instructions than EXP would be required in the group.
+            // Abort the groupping.
+            return;
+        }
+      }
+
+      ExpGroup.push_back(SUNum);
+    }
+  }
+
+  // The group can be formed. Give the color.
+  for (unsigned j : ExpGroup)
+    CurrentColoring[j] = ExportColor;
+}
+
 void SIScheduleBlockCreator::createBlocksForVariant(SISchedulerBlockCreatorVariant BlockVariant) {
   unsigned DAGSize = DAG->SUnits.size();
   std::map<unsigned,unsigned> RealID;
@@ -1159,6 +1215,7 @@
   regroupNoUserInstructions();
   colorMergeConstantLoadsNextGroup();
   colorMergeIfPossibleNextGroupOnlyForReserved();
+  colorExports();
 
   // Put SUs of same color into same block
   Node2CurrentBlock.resize(DAGSize, -1);
Index: llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.h
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.h
+++ llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.h
@@ -302,6 +302,9 @@
   // (we'd want these groups be at the end).
   void regroupNoUserInstructions();
 
+  // Give Reserved color to export instructions
+  void colorExports();
+
   void createBlocksForVariant(SISchedulerBlockCreatorVariant BlockVariant);
 
   void topologicalSort();


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