[PATCH] D35839: [X86] SET0 to use XMM registers where possible PR26018 PR32862

[Elena Demikhovsky via Phabricator via llvm-commits]

delena added a comment.

In https://reviews.llvm.org/D35839#820377, @RKSimon wrote:

> In https://reviews.llvm.org/D35839#820306, @delena wrote:
>
> > We have EVEX to VEX pass to shorten the encoding. But you replaced ymm with xmm. I don't understand why it's better.
>
>
> This came up on PR32862, which was mainly about AMD 128-bit SIMD ALUs being able to create fewer uops in 256-bit vector code by making use of VEX implicit zeroing of the upper subvectors. Is there any benefit to using xmm on AVX512 hardware or would ymm be better?


There is no any diff between xmm and ymm on Intel processors, AFAIK.
I was wrong talking about EVEX2VEX pass, btw. It will do nothing with zmm.
Do AMD processors support AVX-512?



================
Comment at: lib/Target/X86/X86InstrInfo.cpp:7743
   case X86::AVX512_512_SET0:
+  {
+    const TargetRegisterInfo *TRI = &getRegisterInfo();
----------------
Please run clang-format on this code.


https://reviews.llvm.org/D35839