[PATCH] D34684: [Power 9] Exploit vector absolute difference instructions on Power 9

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.

I think the comments are minor enough that they can be addressed on the commit. LGTM.



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Comment at: lib/Target/PowerPC/PPCInstrAltivec.td:1489
+
+def : Pat<(v16i8:$vD (int_ppc_altivec_vabsdub v16i8:$vA, v16i8:$vB)),
+          (v16i8(VABSDUB $vA, $vB))>;
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I don't see a compelling reason to remove these patterns from the instruction defs just to add them as anonymous patterns. The instruction definitions should remain unchanged.


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Comment at: lib/Target/PowerPC/PPCInstrAltivec.td:1497
+def : Pat<(v16i8:$vD (abs v16i8:$vA)),
+          (v16i8(VABSDUB $vA, (V_SET0B)))>;
+def : Pat<(v8i16:$vD (abs v8i16:$vA)),
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Formatting nit: please add a space between the type and the left paren:
`(v16i8 (VABSDUB...`
of course, this applies for all of these output patterns suffering from the same issue.


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Comment at: test/CodeGen/PowerPC/ppc64-P9-vabsd.ll:9
+  %sub.i = sub <4 x i32> zeroinitializer, %a
+  %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %a, <4 x i32> %sub.i)
+  ret <4 x i32> %0
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Please add a test case where the `sub(0, a)` is the first operand to the max intrinsic for symmetry.


https://reviews.llvm.org/D34684