[PATCH] D34990: Fix endianness bug in DAGCombiner::visitTRUNCATE and visitEXTRACT_VECTOR_ELT

[Francois Pichet via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL308960: Fix endianness bug in DAGCombiner::visitTRUNCATE and visitEXTRACT_VECTOR_ELT (authored by fpichet).

Changed prior to commit:
  https://reviews.llvm.org/D34990?vs=106137&id=108028#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D34990

Files:
  llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/trunk/test/CodeGen/Mips/pr33682.ll


Index: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8500,7 +8500,7 @@
   // Fold truncate of a bitcast of a vector to an extract of the low vector
   // element.
   //
-  // e.g. trunc (i64 (bitcast v2i32:x)) -> extract_vector_elt v2i32:x, 0
+  // e.g. trunc (i64 (bitcast v2i32:x)) -> extract_vector_elt v2i32:x, idx
   if (N0.getOpcode() == ISD::BITCAST && !VT.isVector()) {
     SDValue VecSrc = N0.getOperand(0);
     EVT SrcVT = VecSrc.getValueType();
@@ -8510,8 +8510,9 @@
       SDLoc SL(N);
 
       EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
+      unsigned Idx = isLE ? 0 : SrcVT.getVectorNumElements() - 1;
       return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, VT,
-                         VecSrc, DAG.getConstant(0, SL, IdxVT));
+                         VecSrc, DAG.getConstant(Idx, SL, IdxVT));
     }
   }
 
@@ -13773,9 +13774,11 @@
     // converts.
   }
 
-  // extract_vector_elt (v2i32 (bitcast i64:x)), 0 -> i32 (trunc i64:x)
+  // extract_vector_elt (v2i32 (bitcast i64:x)), EltTrunc -> i32 (trunc i64:x)
+  bool isLE = DAG.getDataLayout().isLittleEndian();
+  unsigned EltTrunc = isLE ? 0 : VT.getVectorNumElements() - 1;
   if (ConstEltNo && InVec.getOpcode() == ISD::BITCAST && InVec.hasOneUse() &&
-      ConstEltNo->isNullValue() && VT.isInteger()) {
+      ConstEltNo->getZExtValue() == EltTrunc && VT.isInteger()) {
     SDValue BCSrc = InVec.getOperand(0);
     if (BCSrc.getValueType().isScalarInteger())
       return DAG.getNode(ISD::TRUNCATE, SDLoc(N), NVT, BCSrc);
Index: llvm/trunk/test/CodeGen/Mips/pr33682.ll
===================================================================
--- llvm/trunk/test/CodeGen/Mips/pr33682.ll
+++ llvm/trunk/test/CodeGen/Mips/pr33682.ll
@@ -0,0 +1,55 @@
+; RUN: llc -march=mips -mcpu=mips32  < %s | FileCheck %s --check-prefixes=ALL,BE
+; RUN: llc -march=mipsel -mcpu=mips32  < %s | FileCheck %s --check-prefixes=ALL,LE
+
+; Verify visitTRUNCATE respects endianness when transforming trunc to insert_vector_elt.
+
+; ALL-LABEL: a:
+; BE: lw $2, 4($4)
+; LE: lw $2, 0($4)
+
+define i32 @a(<2 x i32> * %a) {
+entry:
+%0 = load <2 x i32>, <2 x i32> * %a
+%1 = bitcast <2 x i32> %0 to i64
+%2 = trunc i64 %1 to i32
+ret i32 %2
+}
+
+; ALL-LABEL: b:
+; BE: lw $2, 12($4)
+; LE: lw $2, 0($4)
+
+define i32 @b(<4 x i32> * %a) {
+entry:
+%0 = load <4 x i32>, <4 x i32> * %a
+%1 = bitcast <4 x i32> %0 to i128
+%2 = trunc i128 %1 to i32
+ret i32 %2
+}
+
+
+; Verify visitEXTRACT_VECTOR_ELT respects endianness when transforming extract_vector_elt to a trunc.
+
+; ALL-LABEL: c:
+; BE: lw $2, 0($4)
+; LE: lw $2, 0($4)
+
+define i32 @c(i64 * %a) {
+entry:
+%0 = load i64, i64 * %a
+%1 = bitcast i64 %0 to <2 x i32>
+%2 = extractelement <2 x i32> %1, i32 0
+ret i32 %2
+}
+
+; ALL-LABEL: d:
+; BE: lw $2, 4($4)
+; LE: lw $2, 4($4)
+
+define i32 @d(i64 * %a) {
+entry:
+%0 = load i64, i64 * %a
+%1 = bitcast i64 %0 to <2 x i32>
+%2 = extractelement <2 x i32> %1, i32 1
+ret i32 %2
+}


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