[PATCH] D35568: [AArch64] Use 8 bytes as preferred function alignment on Cortex-A53.

[Renato Golin via Phabricator via llvm-commits]

rengolin added a comment.

In https://reviews.llvm.org/D35568#818708, @fhahn wrote:

> Using 8 byte alignment gives a 0.25% speedup on execution time (was 0.23% with 16 bytes), a 0.82% improvement
>  in benchmark scores  (was 0.93% with 16 bytes) and  a 0.20% increase in binary size (was 0.55%). So for the score related benchmarks, the 8 byte alignment makes things worse quite a bit, but the impact on size is much smaller. Should we use 8 byte alignment, to keep the binary size down?


I wouldn't rely too much on LLVM's "benchmarking" suite. They're good to spot regressions, but not very representative of all things. The reduction in code size is higher than in performance, so I think that's a win.

@davide, comments on the new code size changes?

cheers,
--renato

PS: A quick EEMBC run would also be interesting, given that we're talking about code size on A53.


https://reviews.llvm.org/D35568