[PATCH] D35749: RA: Remove another assert on empty intervals

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
Herald added subscribers: eraman, nhaehnle, wdng.

This case is similar to the one fixed in r308808,
except when rematerializing.

      

Fixes bug 33884.


https://reviews.llvm.org/D35749

Files:
  lib/CodeGen/InlineSpiller.cpp
  test/CodeGen/AMDGPU/spill-empty-live-interval.mir


Index: test/CodeGen/AMDGPU/spill-empty-live-interval.mir
===================================================================
--- test/CodeGen/AMDGPU/spill-empty-live-interval.mir
+++ test/CodeGen/AMDGPU/spill-empty-live-interval.mir
@@ -38,3 +38,37 @@
     S_ENDPGM
 
 ...
+
+# Similar assert which happens when trying to rematerialize.
+# https://bugs.llvm.org/show_bug.cgi?id=33884
+---
+# CHECK-LABEL: name: rematerialize_empty_interval_has_reference
+
+# CHECK-NOT: MOV
+# CHECK: undef %3.sub2 = V_MOV_B32_e32 1786773504, implicit %exec
+
+# CHECK: bb.1:
+# CHECK-NEXT: S_NOP 0, implicit %3.sub2
+# CHECK-NEXT: S_NOP 0, implicit undef %6.sub0
+# CHECK-NEXT: undef %4.sub2 = V_MOV_B32_e32 0, implicit %exec
+# CHECK-NEXT: S_NOP 0, implicit %4.sub2
+name: rematerialize_empty_interval_has_reference
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vreg_128, preferred-register: '' }
+  - { id: 1, class: vgpr_32, preferred-register: '' }
+  - { id: 2, class: vgpr_32, preferred-register: '' }
+  - { id: 3, class: vreg_128, preferred-register: '' }
+body:             |
+  bb.0:
+    successors: %bb.1
+
+    undef %0.sub2 = V_MOV_B32_e32 0, implicit %exec
+    undef %3.sub2 = V_MOV_B32_e32 1786773504, implicit %exec
+
+  bb.1:
+    S_NOP 0, implicit %3.sub2
+    S_NOP 0, implicit undef %0.sub0
+    S_NOP 0, implicit %0.sub2
+
+...
Index: lib/CodeGen/InlineSpiller.cpp
===================================================================
--- lib/CodeGen/InlineSpiller.cpp
+++ lib/CodeGen/InlineSpiller.cpp
@@ -643,8 +643,8 @@
       Edit->eraseVirtReg(Reg);
       continue;
     }
-    assert((LIS.hasInterval(Reg) && !LIS.getInterval(Reg).empty()) &&
-           "Reg with empty interval has reference");
+
+    assert(LIS.hasInterval(Reg) && "Reg with no interval");
     RegsToSpill[ResultPos++] = Reg;
   }
   RegsToSpill.erase(RegsToSpill.begin() + ResultPos, RegsToSpill.end());


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