[llvm] r308779 - AMDGPU: Introduce maybeAtomic instruction flag
Konstantin Zhuravlyov via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 21 14:05:45 PDT 2017
Author: kzhuravl
Date: Fri Jul 21 14:05:45 2017
New Revision: 308779
URL: http://llvm.org/viewvc/llvm-project?rev=308779&view=rev
Log:
AMDGPU: Introduce maybeAtomic instruction flag
Testing is in the follow up change
Modified:
llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td
llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td
llvm/trunk/lib/Target/AMDGPU/SIDefines.h
llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td
llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
Modified: llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td?rev=308779&r1=308778&r2=308779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td Fri Jul 21 14:05:45 2017
@@ -437,6 +437,7 @@ class MUBUF_Load_Pseudo <string opName,
let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
let mayLoad = 1;
let mayStore = 0;
+ let maybeAtomic = 1;
}
// FIXME: tfe can't be an operand because it requires a separate
@@ -483,6 +484,7 @@ class MUBUF_Store_Pseudo <string opName,
let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
let mayLoad = 0;
let mayStore = 1;
+ let maybeAtomic = 1;
}
multiclass MUBUF_Pseudo_Stores<string opName, RegisterClass vdataClass,
@@ -566,6 +568,7 @@ class MUBUF_Atomic_Pseudo<string opName,
let DisableWQM = 1;
let has_glc = 0;
let has_tfe = 0;
+ let maybeAtomic = 1;
}
class MUBUF_AtomicNoRet_Pseudo<string opName, int addrKind,
Modified: llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td?rev=308779&r1=308778&r2=308779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td Fri Jul 21 14:05:45 2017
@@ -137,6 +137,7 @@ class FLAT_Load_Pseudo <string opName, R
let has_saddr = HasSaddr;
let enabled_saddr = EnableSaddr;
let PseudoInstr = opName#!if(!and(HasSaddr, EnableSaddr), "_SADDR", "");
+ let maybeAtomic = 1;
}
class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass,
@@ -157,6 +158,7 @@ class FLAT_Store_Pseudo <string opName,
let has_saddr = HasSaddr;
let enabled_saddr = EnableSaddr;
let PseudoInstr = opName#!if(!and(HasSaddr, EnableSaddr), "_SADDR", "");
+ let maybeAtomic = 1;
}
multiclass FLAT_Global_Load_Pseudo<string opName, RegisterClass regClass> {
@@ -187,6 +189,7 @@ class FLAT_Scratch_Load_Pseudo <string o
let enabled_saddr = EnableSaddr;
let has_vaddr = !if(EnableSaddr, 0, 1);
let PseudoInstr = opName#!if(EnableSaddr, "_SADDR", "");
+ let maybeAtomic = 1;
}
class FLAT_Scratch_Store_Pseudo <string opName, RegisterClass vdataClass, bit EnableSaddr = 0> : FLAT_Pseudo<
@@ -202,8 +205,8 @@ class FLAT_Scratch_Store_Pseudo <string
let has_saddr = 1;
let enabled_saddr = EnableSaddr;
let has_vaddr = !if(EnableSaddr, 0, 1);
-
let PseudoInstr = opName#!if(EnableSaddr, "_SADDR", "");
+ let maybeAtomic = 1;
}
multiclass FLAT_Scratch_Load_Pseudo<string opName, RegisterClass regClass> {
@@ -228,6 +231,7 @@ class FLAT_AtomicNoRet_Pseudo<string opN
let has_glc = 0;
let glcValue = 0;
let has_vdst = 0;
+ let maybeAtomic = 1;
}
class FLAT_AtomicRet_Pseudo<string opName, dag outs, dag ins,
Modified: llvm/trunk/lib/Target/AMDGPU/SIDefines.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIDefines.h?rev=308779&r1=308778&r2=308779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIDefines.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIDefines.h Fri Jul 21 14:05:45 2017
@@ -68,7 +68,8 @@ enum : uint64_t {
FIXED_SIZE = UINT64_C(1) << 40,
VOPAsmPrefer32Bit = UINT64_C(1) << 41,
HasFPClamp = UINT64_C(1) << 42,
- VOP3_OPSEL = UINT64_C(1) << 43
+ VOP3_OPSEL = UINT64_C(1) << 43,
+ maybeAtomic = UINT64_C(1) << 44
};
// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td?rev=308779&r1=308778&r2=308779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td Fri Jul 21 14:05:45 2017
@@ -45,7 +45,7 @@ class InstSI <dag outs, dag ins, string
field bit FLAT = 0;
field bit DS = 0;
- // Pseudo instruction formats.
+ // Pseudo instruction formats.
field bit VGPRSpill = 0;
field bit SGPRSpill = 0;
@@ -87,6 +87,9 @@ class InstSI <dag outs, dag ins, string
// modifier (gfx9 only).
field bit VOP3_OPSEL = 0;
+ // Is it possible for this instruction to be atomic?
+ field bit maybeAtomic = 0;
+
// These need to be kept in sync with the enum in SIInstrFlags.
let TSFlags{0} = SALU;
let TSFlags{1} = VALU;
@@ -133,6 +136,8 @@ class InstSI <dag outs, dag ins, string
let TSFlags{42} = FPClamp;
let TSFlags{43} = VOP3_OPSEL;
+ let TSFlags{44} = maybeAtomic;
+
let SchedRW = [Write32Bit];
field bits<1> DisableSIDecoder = 0;
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=308779&r1=308778&r2=308779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Fri Jul 21 14:05:45 2017
@@ -99,6 +99,7 @@ def ATOMIC_FENCE : SPseudoInstSI<
[(atomic_fence (i32 imm:$ordering), (i32 imm:$scope))],
"ATOMIC_FENCE $ordering, $scope"> {
let hasSideEffects = 1;
+ let maybeAtomic = 1;
}
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in {
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