[llvm] r308761 - [Hexagon] Add inline-asm constraint 'a' for modifier register class

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Fri Jul 21 10:51:27 2017
New Revision: 308761

URL: http://llvm.org/viewvc/llvm-project?rev=308761&view=rev
Log:
[Hexagon] Add inline-asm constraint 'a' for modifier register class

For example
  asm ("memw(%0++%1) = %2" : : "r"(addr),"a"(mod),"r"(val) : "memory")

Added:
    llvm/trunk/test/CodeGen/Hexagon/inline-asm-a.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=308761&r1=308760&r2=308761&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Fri Jul 21 10:51:27 2017
@@ -2923,7 +2923,11 @@ HexagonTargetLowering::getConstraintType
       case 'q':
       case 'v':
         if (Subtarget.useHVXOps())
-          return C_Register;
+          return C_RegisterClass;
+        break;
+      case 'a':
+        return C_RegisterClass;
+      default:
         break;
     }
   }
@@ -2951,6 +2955,9 @@ HexagonTargetLowering::getRegForInlineAs
       case MVT::f64:
         return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
       }
+      break;
+    case 'a': // M0-M1
+      return std::make_pair(0U, &Hexagon::ModRegsRegClass);
     case 'q': // q0-q3
       switch (VT.getSizeInBits()) {
       default:
@@ -2960,6 +2967,7 @@ HexagonTargetLowering::getRegForInlineAs
       case 1024:
         return std::make_pair(0U, &Hexagon::VecPredRegs128BRegClass);
       }
+      break;
     case 'v': // V0-V31
       switch (VT.getSizeInBits()) {
       default:
@@ -2973,7 +2981,7 @@ HexagonTargetLowering::getRegForInlineAs
       case 2048:
         return std::make_pair(0U, &Hexagon::VecDblRegs128BRegClass);
       }
-
+      break;
     default:
       llvm_unreachable("Unknown asm register class");
     }

Added: llvm/trunk/test/CodeGen/Hexagon/inline-asm-a.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/inline-asm-a.ll?rev=308761&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/inline-asm-a.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/inline-asm-a.ll Fri Jul 21 10:51:27 2017
@@ -0,0 +1,16 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Check that constraint a is handled correctly.
+; CHECK: [[M:m[01]]] = r1
+; CHECK: memw(r0++[[M]]) = r2
+
+target triple = "hexagon"
+
+; Function Attrs: nounwind
+define void @foo(i32* %a, i32 %m, i32 %v) #0 {
+entry:
+  tail call void asm sideeffect "memw($0++$1) = $2", "r,a,r,~{memory}"(i32* %a, i32 %m, i32 %v)
+  ret void
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv60" }