[llvm] r308673 - Add an ID field to StackObjects
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 20 14:03:45 PDT 2017
Author: arsenm
Date: Thu Jul 20 14:03:45 2017
New Revision: 308673
URL: http://llvm.org/viewvc/llvm-project?rev=308673&view=rev
Log:
Add an ID field to StackObjects
On AMDGPU SGPR spills are really spilled to another register.
The spiller creates the spills to new frame index objects,
which is used as a placeholder.
This will eventually be replaced with a reference to a position
in a VGPR to write to and the frame index deleted. It is
most likely not a real stack location that can be shared
with another stack object.
This is a problem when StackSlotColoring decides it should
combine a frame index used for a normal VGPR spill with
a real stack location and a frame index used for an SGPR.
Add an ID field so that StackSlotColoring has a way
of knowing the different frame index types are
incompatible.
Added:
llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
llvm/trunk/test/CodeGen/MIR/AMDGPU/stack-id.mir
Modified:
llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h
llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h
llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/trunk/lib/CodeGen/MIRPrinter.cpp
llvm/trunk/lib/CodeGen/MachineFrameInfo.cpp
llvm/trunk/lib/CodeGen/MachineInstr.cpp
llvm/trunk/lib/CodeGen/StackSlotColoring.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll
llvm/trunk/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir
llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir
llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-objects.mir
llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
llvm/trunk/test/CodeGen/MIR/X86/stack-objects.mir
llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll
Modified: llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=308673&r1=308672&r2=308673&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h Thu Jul 20 14:03:45 2017
@@ -202,6 +202,7 @@ struct MachineStackObject {
int64_t Offset = 0;
uint64_t Size = 0;
unsigned Alignment = 0;
+ uint8_t StackID = 0;
StringValue CalleeSavedRegister;
Optional<int64_t> LocalOffset;
StringValue DebugVar;
@@ -211,6 +212,7 @@ struct MachineStackObject {
return ID == Other.ID && Name == Other.Name && Type == Other.Type &&
Offset == Other.Offset && Size == Other.Size &&
Alignment == Other.Alignment &&
+ StackID == Other.StackID &&
CalleeSavedRegister == Other.CalleeSavedRegister &&
LocalOffset == Other.LocalOffset && DebugVar == Other.DebugVar &&
DebugExpr == Other.DebugExpr && DebugLoc == Other.DebugLoc;
@@ -237,6 +239,7 @@ template <> struct MappingTraits<Machine
if (Object.Type != MachineStackObject::VariableSized)
YamlIO.mapRequired("size", Object.Size);
YamlIO.mapOptional("alignment", Object.Alignment, (unsigned)0);
+ YamlIO.mapOptional("stack-id", Object.StackID);
YamlIO.mapOptional("callee-saved-register", Object.CalleeSavedRegister,
StringValue()); // Don't print it out when it's empty.
YamlIO.mapOptional("local-offset", Object.LocalOffset, Optional<int64_t>());
@@ -260,12 +263,14 @@ struct FixedMachineStackObject {
int64_t Offset = 0;
uint64_t Size = 0;
unsigned Alignment = 0;
+ uint8_t StackID = 0;
bool IsImmutable = false;
bool IsAliased = false;
StringValue CalleeSavedRegister;
bool operator==(const FixedMachineStackObject &Other) const {
return ID == Other.ID && Type == Other.Type && Offset == Other.Offset &&
Size == Other.Size && Alignment == Other.Alignment &&
+ StackID == Other.StackID &&
IsImmutable == Other.IsImmutable && IsAliased == Other.IsAliased &&
CalleeSavedRegister == Other.CalleeSavedRegister;
}
@@ -289,6 +294,7 @@ template <> struct MappingTraits<FixedMa
YamlIO.mapOptional("offset", Object.Offset, (int64_t)0);
YamlIO.mapOptional("size", Object.Size, (uint64_t)0);
YamlIO.mapOptional("alignment", Object.Alignment, (unsigned)0);
+ YamlIO.mapOptional("stack-id", Object.StackID);
if (Object.Type != FixedMachineStackObject::SpillSlot) {
YamlIO.mapOptional("isImmutable", Object.IsImmutable, false);
YamlIO.mapOptional("isAliased", Object.IsAliased, false);
Modified: llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h?rev=308673&r1=308672&r2=308673&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h Thu Jul 20 14:03:45 2017
@@ -99,9 +99,17 @@ class MachineFrameInfo {
/// and/or GC related) over a statepoint. We know that the address of the
/// slot can't alias any LLVM IR value. This is very similar to a Spill
/// Slot, but is created by statepoint lowering is SelectionDAG, not the
- /// register allocator.
+ /// register allocator.
bool isStatepointSpillSlot;
+ /// Identifier for stack memory type analagous to address space. If this is
+ /// non-0, the meaning is target defined. Offsets cannot be directly
+ /// compared between objects with different stack IDs. The object may not
+ /// necessarily reside in the same contiguous memory block as other stack
+ /// objects. Objects with differing stack IDs should not be merged or
+ /// replaced substituted for each other.
+ uint8_t StackID;
+
/// If this stack object is originated from an Alloca instruction
/// this value saves the original IR allocation. Can be NULL.
const AllocaInst *Alloca;
@@ -123,10 +131,11 @@ class MachineFrameInfo {
bool isSExt;
StackObject(uint64_t Sz, unsigned Al, int64_t SP, bool IM,
- bool isSS, const AllocaInst *Val, bool A)
+ bool isSS, const AllocaInst *Val, bool Aliased, uint8_t ID = 0)
: SPOffset(SP), Size(Sz), Alignment(Al), isImmutable(IM),
- isSpillSlot(isSS), isStatepointSpillSlot(false), Alloca(Val),
- PreAllocated(false), isAliased(A), isZExt(false), isSExt(false) {}
+ isSpillSlot(isSS), isStatepointSpillSlot(false), StackID(ID),
+ Alloca(Val),
+ PreAllocated(false), isAliased(Aliased), isZExt(false), isSExt(false) {}
};
/// The alignment of the stack.
@@ -600,6 +609,18 @@ public:
return Objects[ObjectIdx+NumFixedObjects].isStatepointSpillSlot;
}
+ /// \see StackID
+ uint8_t getStackID(int ObjectIdx) const {
+ return Objects[ObjectIdx+NumFixedObjects].StackID;
+ }
+
+ /// \see StackID
+ void setStackID(int ObjectIdx, uint8_t ID) {
+ assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() &&
+ "Invalid Object Idx!");
+ Objects[ObjectIdx+NumFixedObjects].StackID = ID;
+ }
+
/// Returns true if the specified index corresponds to a dead object.
bool isDeadObjectIndex(int ObjectIdx) const {
assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() &&
@@ -625,7 +646,7 @@ public:
/// Create a new statically sized stack object, returning
/// a nonnegative identifier to represent it.
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS,
- const AllocaInst *Alloca = nullptr);
+ const AllocaInst *Alloca = nullptr, uint8_t ID = 0);
/// Create a new statically sized stack object that represents a spill slot,
/// returning a nonnegative identifier to represent it.
Modified: llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h?rev=308673&r1=308672&r2=308673&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h Thu Jul 20 14:03:45 2017
@@ -45,18 +45,23 @@ struct MachinePointerInfo {
/// Offset - This is an offset from the base Value*.
int64_t Offset;
- explicit MachinePointerInfo(const Value *v = nullptr, int64_t offset = 0)
- : V(v), Offset(offset) {}
+ uint8_t StackID;
+
+ explicit MachinePointerInfo(const Value *v = nullptr, int64_t offset = 0,
+ uint8_t ID = 0)
+ : V(v), Offset(offset), StackID(ID) {}
explicit MachinePointerInfo(const PseudoSourceValue *v,
- int64_t offset = 0)
- : V(v), Offset(offset) {}
+ int64_t offset = 0,
+ uint8_t ID = 0)
+ : V(v), Offset(offset), StackID(ID) {}
MachinePointerInfo getWithOffset(int64_t O) const {
if (V.isNull()) return MachinePointerInfo();
if (V.is<const Value*>())
- return MachinePointerInfo(V.get<const Value*>(), Offset+O);
- return MachinePointerInfo(V.get<const PseudoSourceValue*>(), Offset+O);
+ return MachinePointerInfo(V.get<const Value*>(), Offset+O, StackID);
+ return MachinePointerInfo(V.get<const PseudoSourceValue*>(), Offset+O,
+ StackID);
}
/// Return true if memory region [V, V+Offset+Size) is known to be
@@ -82,7 +87,8 @@ struct MachinePointerInfo {
static MachinePointerInfo getGOT(MachineFunction &MF);
/// Stack pointer relative access.
- static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset);
+ static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset,
+ uint8_t ID = 0);
};
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=308673&r1=308672&r2=308673&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp Thu Jul 20 14:03:45 2017
@@ -587,6 +587,7 @@ bool MIRParserImpl::initializeFrameInfo(
else
ObjectIdx = MFI.CreateFixedSpillStackObject(Object.Size, Object.Offset);
MFI.setObjectAlignment(ObjectIdx, Object.Alignment);
+ MFI.setStackID(ObjectIdx, Object.StackID);
if (!PFS.FixedStackObjectSlots.insert(std::make_pair(Object.ID.Value,
ObjectIdx))
.second)
@@ -619,6 +620,8 @@ bool MIRParserImpl::initializeFrameInfo(
Object.Size, Object.Alignment,
Object.Type == yaml::MachineStackObject::SpillSlot, Alloca);
MFI.setObjectOffset(ObjectIdx, Object.Offset);
+ MFI.setStackID(ObjectIdx, Object.StackID);
+
if (!PFS.StackObjectSlots.insert(std::make_pair(Object.ID.Value, ObjectIdx))
.second)
return error(Object.ID.SourceRange.Start,
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=308673&r1=308672&r2=308673&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Thu Jul 20 14:03:45 2017
@@ -366,6 +366,7 @@ void MIRPrinter::convertStackObjects(yam
YamlObject.Offset = MFI.getObjectOffset(I);
YamlObject.Size = MFI.getObjectSize(I);
YamlObject.Alignment = MFI.getObjectAlignment(I);
+ YamlObject.StackID = MFI.getStackID(I);
YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
YMF.FixedStackObjects.push_back(YamlObject);
@@ -392,6 +393,7 @@ void MIRPrinter::convertStackObjects(yam
YamlObject.Offset = MFI.getObjectOffset(I);
YamlObject.Size = MFI.getObjectSize(I);
YamlObject.Alignment = MFI.getObjectAlignment(I);
+ YamlObject.StackID = MFI.getStackID(I);
YMF.StackObjects.push_back(YamlObject);
StackObjectOperandMapping.insert(std::make_pair(
Modified: llvm/trunk/lib/CodeGen/MachineFrameInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFrameInfo.cpp?rev=308673&r1=308672&r2=308673&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineFrameInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineFrameInfo.cpp Thu Jul 20 14:03:45 2017
@@ -47,11 +47,12 @@ static inline unsigned clampStackAlignme
}
int MachineFrameInfo::CreateStackObject(uint64_t Size, unsigned Alignment,
- bool isSS, const AllocaInst *Alloca) {
+ bool isSS, const AllocaInst *Alloca,
+ uint8_t ID) {
assert(Size != 0 && "Cannot allocate zero size stack objects!");
Alignment = clampStackAlignment(!StackRealignable, Alignment, StackAlignment);
Objects.push_back(StackObject(Size, Alignment, 0, false, isSS, Alloca,
- !isSS));
+ !isSS, ID));
int Index = (int)Objects.size() - NumFixedObjects - 1;
assert(Index >= 0 && "Bad frame index!");
ensureMaxAlignment(Alignment);
@@ -212,6 +213,10 @@ void MachineFrameInfo::print(const Machi
for (unsigned i = 0, e = Objects.size(); i != e; ++i) {
const StackObject &SO = Objects[i];
OS << " fi#" << (int)(i-NumFixedObjects) << ": ";
+
+ if (SO.StackID != 0)
+ OS << "id=" << SO.StackID << ' ';
+
if (SO.Size == ~0ULL) {
OS << "dead\n";
continue;
Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=308673&r1=308672&r2=308673&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Thu Jul 20 14:03:45 2017
@@ -609,8 +609,9 @@ MachinePointerInfo MachinePointerInfo::g
}
MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
- int64_t Offset) {
- return MachinePointerInfo(MF.getPSVManager().getStack(), Offset);
+ int64_t Offset,
+ uint8_t ID) {
+ return MachinePointerInfo(MF.getPSVManager().getStack(), Offset,ID);
}
MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
Modified: llvm/trunk/lib/CodeGen/StackSlotColoring.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackSlotColoring.cpp?rev=308673&r1=308672&r2=308673&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/StackSlotColoring.cpp (original)
+++ llvm/trunk/lib/CodeGen/StackSlotColoring.cpp Thu Jul 20 14:03:45 2017
@@ -233,6 +233,8 @@ StackSlotColoring::OverlapWithAssignment
int StackSlotColoring::ColorSlot(LiveInterval *li) {
int Color = -1;
bool Share = false;
+ int FI = TargetRegisterInfo::stackSlot2Index(li->reg);
+
if (!DisableSharing) {
// Check if it's possible to reuse any of the used colors.
Color = UsedColors.find_first();
@@ -246,6 +248,11 @@ int StackSlotColoring::ColorSlot(LiveInt
}
}
+ if (Color != -1 && MFI->getStackID(Color) != MFI->getStackID(FI)) {
+ DEBUG(dbgs() << "cannot share FIs with different stack IDs\n");
+ Share = false;
+ }
+
// Assign it to the first available color (assumed to be the best) if it's
// not possible to share a used color with other objects.
if (!Share) {
@@ -257,7 +264,6 @@ int StackSlotColoring::ColorSlot(LiveInt
// Record the assignment.
Assignments[Color].push_back(li);
- int FI = TargetRegisterInfo::stackSlot2Index(li->reg);
DEBUG(dbgs() << "Assigning fi#" << FI << " to fi#" << Color << "\n");
// Change size and alignment of the allocated slot. If there are multiple
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=308673&r1=308672&r2=308673&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Thu Jul 20 14:03:45 2017
@@ -768,6 +768,7 @@ void SIInstrInfo::storeRegToStackSlot(Ma
// needing them, and need to ensure that the reserved registers are
// correctly handled.
+ FrameInfo.setStackID(FrameIndex, 1);
if (ST.hasScalarStores()) {
// m0 is used for offset to scalar stores if used to spill.
Spill.addReg(AMDGPU::M0, RegState::ImplicitDefine | RegState::Dead);
@@ -863,6 +864,7 @@ void SIInstrInfo::loadRegFromStackSlot(M
MRI.constrainRegClass(DestReg, &AMDGPU::SReg_32_XM0RegClass);
}
+ FrameInfo.setStackID(FrameIndex, 1);
MachineInstrBuilder Spill = BuildMI(MBB, MI, DL, OpDesc, DestReg)
.addFrameIndex(FrameIndex) // addr
.addMemOperand(MMO)
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll?rev=308673&r1=308672&r2=308673&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll Thu Jul 20 14:03:45 2017
@@ -11,7 +11,7 @@ target triple = "aarch64--"
; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_ADD [[ARG1]], [[ARG2]]
; CHECK-NEXT: %x0 = COPY [[RES]]
-; CHECK-NEXT: RET_ReallyLR implicit %x0
+; CHECK-NEXT: RET_ReallyLR implicit %x0
define i64 @addi64(i64 %arg1, i64 %arg2) {
%res = add i64 %arg1, %arg2
ret i64 %res
@@ -32,11 +32,14 @@ define i64 @muli64(i64 %arg1, i64 %arg2)
; CHECK-LABEL: name: allocai64
; CHECK: stack:
; CHECK-NEXT: - { id: 0, name: ptr1, type: default, offset: 0, size: 8, alignment: 8,
-; CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+; CHECK-NEXT: stack-id: 0, callee-saved-register: '', di-variable: '', di-expression: '',
+; CHECK-NEXT: di-location: '' }
; CHECK-NEXT: - { id: 1, name: ptr2, type: default, offset: 0, size: 8, alignment: 1,
-; CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+; CHECK-NEXT: stack-id: 0, callee-saved-register: '', di-variable: '', di-expression: '',
+; CHECK-NEXT: di-location: '' }
; CHECK-NEXT: - { id: 2, name: ptr3, type: default, offset: 0, size: 128, alignment: 8,
-; CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+; CHECK-NEXT: stack-id: 0, callee-saved-register: '', di-variable: '', di-expression: '',
+; CHECK-NEXT: di-location: '' }
; CHECK-NEXT: - { id: 3, name: ptr4, type: default, offset: 0, size: 1, alignment: 8,
; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.0.ptr1
; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.1.ptr2
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll?rev=308673&r1=308672&r2=308673&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll Thu Jul 20 14:03:45 2017
@@ -208,7 +208,8 @@ define void @test_call_stack() {
; CHECK-LABEL: name: test_mem_i1
; CHECK: fixedStack:
-; CHECK-NEXT: - { id: [[SLOT:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, isImmutable: true,
+; CHECK-NEXT: - { id: [[SLOT:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, stack-id: 0,
+; CHECK-NEXT: isImmutable: true,
; CHECK: [[ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[SLOT]]
; CHECK: {{%[0-9]+}}(s1) = G_LOAD [[ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[SLOT]], align 0)
define void @test_mem_i1([8 x i64], i1 %in) {
Added: llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir?rev=308673&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir Thu Jul 20 14:03:45 2017
@@ -0,0 +1,34 @@
+# RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -stress-regalloc=1 -start-before=greedy -stop-after=stack-slot-coloring -o - %s | FileCheck %s
+---
+
+# CHECK-LABEL: name: no_merge_sgpr_vgpr_spill_slot{{$}}
+# CHECK: stack:
+# CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
+# CHECK-NEXT: stack-id: 0,
+
+# CHECK: - { id: 1, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
+# CHECK-NEXT: stack-id: 1,
+
+# CHECK: SI_SPILL_V32_SAVE killed %vgpr0, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 4 into %stack.0)
+# CHECK: %vgpr0 = SI_SPILL_V32_RESTORE %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (load 4 from %stack.0)
+
+# CHECK: SI_SPILL_S32_SAVE killed %sgpr6, %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (store 4 into %stack.1)
+# CHECK: %sgpr6 = SI_SPILL_S32_RESTORE %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (load 4 from %stack.1)
+
+name: no_merge_sgpr_vgpr_spill_slot
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vgpr_32 }
+ - { id: 1, class: sreg_32_xm0_xexec }
+ - { id: 2, class: vgpr_32 }
+ - { id: 3, class: sreg_32_xm0_xexec }
+
+body: |
+ bb.0:
+ %0 = FLAT_LOAD_DWORD undef %vgpr0_vgpr1, 0, 0, 0, implicit %flat_scr, implicit %exec
+ %2 = FLAT_LOAD_DWORD undef %vgpr0_vgpr1, 0, 0, 0, implicit %flat_scr, implicit %exec
+ S_NOP 0, implicit %0
+ %1 = S_LOAD_DWORD_IMM undef %sgpr0_sgpr1, 0, 0
+ %3 = S_LOAD_DWORD_IMM undef %sgpr0_sgpr1, 0, 0
+ S_NOP 0, implicit %1
+...
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir?rev=308673&r1=308672&r2=308673&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir Thu Jul 20 14:03:45 2017
@@ -25,9 +25,9 @@ frameInfo:
maxAlignment: 8
# CHECK-LABEL: stack_local
# CHECK: stack:
-# CHECK-NEXT: { id: 0, name: local_var, type: default, offset: 0, size: 8, alignment: 8,
-# CHECK-NEXT: callee-saved-register: '', local-offset: -8, di-variable: '', di-expression: '',
-# CHECK-NEXT: di-location: '' }
+# CHECK: - { id: 0, name: local_var, type: default, offset: 0, size: 8, alignment: 8,
+# CHECK-NEXT: stack-id: 0, callee-saved-register: '', local-offset: -8, di-variable: '',
+# CHECK-NEXT: di-expression: '', di-location: '' }
stack:
- { id: 0,name: local_var,offset: 0,size: 8,alignment: 8, local-offset: -8 }
body: |
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/stack-id.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/stack-id.mir?rev=308673&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/stack-id.mir (added)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/stack-id.mir Thu Jul 20 14:03:45 2017
@@ -0,0 +1,35 @@
+# RUN: llc -march=amdgcn -run-pass none -o - %s | FileCheck %s
+...
+---
+
+# CHECK-LABEL: name: spill_slot_stack_id
+# CHECK: {{^}}fixedStack:
+# CHECK: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4, stack-id: 0,
+# CHECK: - { id: 1, type: spill-slot, offset: 0, size: 8, alignment: 4, stack-id: 0,
+# CHECK: - { id: 2, type: spill-slot, offset: 0, size: 16, alignment: 4, stack-id: 9,
+
+# CHECK: {{^}}stack:
+# CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 16,
+# CHECK-NEXT: stack-id: 3,
+
+# CHECK: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8,
+# CHECK-NEXT: stack-id: 0,
+
+# CHECK: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4,
+# CHECK-NEXT: stack-id: 0,
+
+
+name: spill_slot_stack_id
+fixedStack:
+ - { id: 0, type: spill-slot, offset: 0, size: 16, alignment: 4, stack-id: 9 }
+ - { id: 1, type: spill-slot, offset: 0, size: 8, alignment: 4, stack-id: 0 }
+ - { id: 2, type: spill-slot, offset: 0, size: 4, alignment: 4 }
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: 0, size: 16, alignment: 4, stack-id: 3 }
+ - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4, stack-id: 0 }
+ - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4 }
+
+body: |
+ bb.0:
+ S_ENDPGM
+...
Modified: llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir?rev=308673&r1=308672&r2=308673&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir Thu Jul 20 14:03:45 2017
@@ -50,7 +50,7 @@ frameInfo:
adjustsStack: true
hasCalls: true
# CHECK: fixedStack:
-# CHECK: , callee-saved-register: '%rbx' }
+# CHECK: callee-saved-register: '%rbx' }
fixedStack:
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%rbx' }
# CHECK: stack:
Modified: llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-objects.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-objects.mir?rev=308673&r1=308672&r2=308673&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-objects.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-objects.mir Thu Jul 20 14:03:45 2017
@@ -20,7 +20,8 @@ frameInfo:
stackSize: 4
maxAlignment: 4
# CHECK: fixedStack:
-# CHECK-NEXT: - { id: 0, type: default, offset: 0, size: 4, alignment: 4, isImmutable: true,
+# CHECK-NEXT: - { id: 0, type: default, offset: 0, size: 4, alignment: 4, stack-id: 0
+# CHECK-NEXT: isImmutable: true,
fixedStack:
- { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
stack:
Modified: llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir?rev=308673&r1=308672&r2=308673&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir Thu Jul 20 14:03:45 2017
@@ -19,7 +19,8 @@ name: test
frameInfo:
maxAlignment: 4
# CHECK: fixedStack:
-# CHECK-NEXT: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4, callee-saved-register: '' }
+# CHECK-NEXT: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4, stack-id: 0,
+# CHECK-NEXT: callee-saved-register: '' }
fixedStack:
- { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4 }
stack:
Modified: llvm/trunk/test/CodeGen/MIR/X86/stack-objects.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-objects.mir?rev=308673&r1=308672&r2=308673&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/stack-objects.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/stack-objects.mir Thu Jul 20 14:03:45 2017
@@ -22,11 +22,14 @@ frameInfo:
maxAlignment: 8
# CHECK: stack:
# CHECK-NEXT: - { id: 0, name: b, type: default, offset: -12, size: 4, alignment: 4,
-# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: stack-id: 0, callee-saved-register: '', di-variable: '', di-expression: '',
+# CHECK-NEXT: di-location: '' }
# CHECK-NEXT: - { id: 1, name: x, type: default, offset: -24, size: 8, alignment: 8,
-# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: stack-id: 0, callee-saved-register: '', di-variable: '', di-expression: '',
+# CHECK-NEXT: di-location: '' }
# CHECK-NEXT: - { id: 2, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
-# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: stack-id: 0, callee-saved-register: '', di-variable: '', di-expression: '',
+# CHECK-NEXT: di-location: '' }
stack:
- { id: 0, name: b, offset: -12, size: 4, alignment: 4 }
- { id: 1, name: x, offset: -24, size: 8, alignment: 8 }
Modified: llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir?rev=308673&r1=308672&r2=308673&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir Thu Jul 20 14:03:45 2017
@@ -25,9 +25,11 @@ frameInfo:
adjustsStack: true
# CHECK: stack:
# CHECK-NEXT: - { id: 0, name: '', type: default, offset: -20, size: 4, alignment: 4,
-# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: stack-id: 0, callee-saved-register: '', di-variable: '', di-expression: '',
+# CHECK-NEXT: di-location: '' }
# CHECK-NEXT: - { id: 1, name: '', type: default, offset: -32, size: 8, alignment: 8,
-# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: stack-id: 0, callee-saved-register: '', di-variable: '', di-expression: '',
+# CHECK-NEXT: di-location: '' }
# CHECK-NEXT: - { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1,
stack:
- { id: 0, offset: -20, size: 4, alignment: 4 }
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll?rev=308673&r1=308672&r2=308673&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll Thu Jul 20 14:03:45 2017
@@ -11,8 +11,12 @@ define i8 @test_i8_args_8(i8 %arg1, i8 %
; ALL-LABEL: name: test_i8_args_8
; X64: fixedStack:
-; X64: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 1, alignment: 8, isImmutable: true,
-; X64: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, isImmutable: true,
+; X64: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 1, alignment: 8,
+; X64-NEXT: isImmutable: true,
+
+; X64: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16,
+; X64-NEXT: isImmutable: true,
+
; X64: liveins: %ecx, %edi, %edx, %esi, %r8d, %r9d
; X64: [[ARG1:%[0-9]+]](s8) = COPY %edi
; X64-NEXT: %{{[0-9]+}}(s8) = COPY %esi
@@ -26,14 +30,30 @@ define i8 @test_i8_args_8(i8 %arg1, i8 %
; X64-NEXT: [[ARG8:%[0-9]+]](s8) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0)
; X32: fixedStack:
-; X32: id: [[STACK28:[0-9]+]], type: default, offset: 28, size: 1, alignment: 4, isImmutable: true,
-; X32: id: [[STACK24:[0-9]+]], type: default, offset: 24, size: 1, alignment: 8, isImmutable: true,
-; X32: id: [[STACK20:[0-9]+]], type: default, offset: 20, size: 1, alignment: 4, isImmutable: true,
-; X32: id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 1, alignment: 16, isImmutable: true,
-; X32: id: [[STACK12:[0-9]+]], type: default, offset: 12, size: 1, alignment: 4, isImmutable: true,
-; X32: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 1, alignment: 8, isImmutable: true,
-; X32: id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 1, alignment: 4, isImmutable: true,
-; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, isImmutable: true,
+; X32: id: [[STACK28:[0-9]+]], type: default, offset: 28, size: 1, alignment: 4,
+; X32-NEXT: isImmutable: true,
+
+; X32: id: [[STACK24:[0-9]+]], type: default, offset: 24, size: 1, alignment: 8,
+; X32-NEXT: isImmutable: true,
+
+; X32: id: [[STACK20:[0-9]+]], type: default, offset: 20, size: 1, alignment: 4,
+; X32-NEXT: isImmutable: true,
+
+; X32: id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 1, alignment: 16,
+; X32-NEXT: isImmutable: true,
+
+; X32: id: [[STACK12:[0-9]+]], type: default, offset: 12, size: 1, alignment: 4,
+; X32-NEXT: isImmutable: true,
+
+; X32: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 1, alignment: 8,
+;X32-NEXT: isImmutable: true,
+
+; X32: id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 1, alignment: 4,
+; X32-NEXT: isImmutable: true,
+
+; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16,
+; X32-NEXT: isImmutable: true,
+
; X32: [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
; X32-NEXT: [[ARG1:%[0-9]+]](s8) = G_LOAD [[ARG1_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0)
; X32-NEXT: [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
@@ -77,8 +97,10 @@ define i32 @test_i32_args_8(i32 %arg1, i
; ALL-LABEL: name: test_i32_args_8
; X64: fixedStack:
-; X64: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 4, alignment: 8, isImmutable: true,
-; X64: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, isImmutable: true,
+; X64: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 4, alignment: 8,
+; X64-NEXT: isImmutable: true,
+; X64: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16,
+; X64-NEXT: isImmutable: true,
; X64: liveins: %ecx, %edi, %edx, %esi, %r8d, %r9d
; X64: [[ARG1:%[0-9]+]](s32) = COPY %edi
; X64-NEXT: %{{[0-9]+}}(s32) = COPY %esi
@@ -92,14 +114,29 @@ define i32 @test_i32_args_8(i32 %arg1, i
; X64-NEXT: [[ARG8:%[0-9]+]](s32) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK8]], align 0)
; X32: fixedStack:
-; X32: id: [[STACK28:[0-9]+]], type: default, offset: 28, size: 4, alignment: 4, isImmutable: true,
-; X32: id: [[STACK24:[0-9]+]], type: default, offset: 24, size: 4, alignment: 8, isImmutable: true,
-; X32: id: [[STACK20:[0-9]+]], type: default, offset: 20, size: 4, alignment: 4, isImmutable: true,
-; X32: id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 4, alignment: 16, isImmutable: true,
-; X32: id: [[STACK12:[0-9]+]], type: default, offset: 12, size: 4, alignment: 4, isImmutable: true,
-; X32: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 4, alignment: 8, isImmutable: true,
-; X32: id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 4, alignment: 4, isImmutable: true,
-; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, isImmutable: true,
+; X32: id: [[STACK28:[0-9]+]], type: default, offset: 28, size: 4, alignment: 4,
+; X32-NEXT: isImmutable: true,
+
+; X32: id: [[STACK24:[0-9]+]], type: default, offset: 24, size: 4, alignment: 8
+; X32-NEXT: isImmutable: true,
+
+; X32: id: [[STACK20:[0-9]+]], type: default, offset: 20, size: 4, alignment: 4
+; X32-NEXT: isImmutable: true,
+
+; X32: id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 4, alignment: 16
+; X32-NEXT: isImmutable: true,
+
+; X32: id: [[STACK12:[0-9]+]], type: default, offset: 12, size: 4, alignment: 4
+; X32-NEXT: isImmutable: true,
+
+; X32: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 4, alignment: 8
+; X32-NEXT: isImmutable: true,
+
+; X32: id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 4, alignment: 4
+; X32-NEXT: isImmutable: true,
+; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16
+; X32-NEXT: isImmutable: true,
+
; X32: [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
; X32-NEXT: [[ARG1:%[0-9]+]](s32) = G_LOAD [[ARG1_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
; X32-NEXT: [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
@@ -142,8 +179,10 @@ define i64 @test_i64_args_8(i64 %arg1, i
; ALL-LABEL: name: test_i64_args_8
; X64: fixedStack:
-; X64: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 8, alignment: 8, isImmutable: true,
-; X64: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 8, alignment: 16, isImmutable: true,
+; X64: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 8, alignment: 8,
+; X64-NEXT: isImmutable: true,
+; X64: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 8, alignment: 16,
+; X64-NEXT: isImmutable: true,
; X64: liveins: %rcx, %rdi, %rdx, %rsi, %r8, %r9
; X64: [[ARG1:%[0-9]+]](s64) = COPY %rdi
; X64-NEXT: %{{[0-9]+}}(s64) = COPY %rsi
@@ -157,22 +196,38 @@ define i64 @test_i64_args_8(i64 %arg1, i
; X64-NEXT: [[ARG8:%[0-9]+]](s64) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK8]], align 0)
; X32: fixedStack:
-; X32: id: [[STACK60:[0-9]+]], type: default, offset: 60, size: 4, alignment: 4, isImmutable: true,
-; X32: id: [[STACK56:[0-9]+]], type: default, offset: 56, size: 4, alignment: 8, isImmutable: true,
-; X32: id: [[STACK52:[0-9]+]], type: default, offset: 52, size: 4, alignment: 4, isImmutable: true,
-; X32: id: [[STACK48:[0-9]+]], type: default, offset: 48, size: 4, alignment: 16, isImmutable: true,
-; X32: id: [[STACK44:[0-9]+]], type: default, offset: 44, size: 4, alignment: 4, isImmutable: true,
-; X32: id: [[STACK40:[0-9]+]], type: default, offset: 40, size: 4, alignment: 8, isImmutable: true,
-; X32: id: [[STACK36:[0-9]+]], type: default, offset: 36, size: 4, alignment: 4, isImmutable: true,
-; X32: id: [[STACK32:[0-9]+]], type: default, offset: 32, size: 4, alignment: 16, isImmutable: true,
-; X32: id: [[STACK28:[0-9]+]], type: default, offset: 28, size: 4, alignment: 4, isImmutable: true,
-; X32: id: [[STACK24:[0-9]+]], type: default, offset: 24, size: 4, alignment: 8, isImmutable: true,
-; X32: id: [[STACK20:[0-9]+]], type: default, offset: 20, size: 4, alignment: 4, isImmutable: true,
-; X32: id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 4, alignment: 16, isImmutable: true,
-; X32: id: [[STACK12:[0-9]+]], type: default, offset: 12, size: 4, alignment: 4, isImmutable: true,
-; X32: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 4, alignment: 8, isImmutable: true,
-; X32: id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 4, alignment: 4, isImmutable: true,
-; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, isImmutable: true,
+; X32: id: [[STACK60:[0-9]+]], type: default, offset: 60, size: 4, alignment: 4,
+; X32-NEXT: isImmutable: true,
+; X32: id: [[STACK56:[0-9]+]], type: default, offset: 56, size: 4, alignment: 8,
+; X32-NEXT: isImmutable: true,
+; X32: id: [[STACK52:[0-9]+]], type: default, offset: 52, size: 4, alignment: 4
+; X32-NEXT: isImmutable: true,
+; X32: id: [[STACK48:[0-9]+]], type: default, offset: 48, size: 4, alignment: 16
+; X32-NEXT: isImmutable: true,
+; X32: id: [[STACK44:[0-9]+]], type: default, offset: 44, size: 4, alignment: 4
+; X32-NEXT: isImmutable: true,
+; X32: id: [[STACK40:[0-9]+]], type: default, offset: 40, size: 4, alignment: 8
+; X32-NEXT: isImmutable: true,
+; X32: id: [[STACK36:[0-9]+]], type: default, offset: 36, size: 4, alignment: 4
+; X32-NEXT: isImmutable: true,
+; X32: id: [[STACK32:[0-9]+]], type: default, offset: 32, size: 4, alignment: 16
+; X32-NEXT: isImmutable: true,
+; X32: id: [[STACK28:[0-9]+]], type: default, offset: 28, size: 4, alignment: 4
+; X32-NEXT: isImmutable: true,
+; X32: id: [[STACK24:[0-9]+]], type: default, offset: 24, size: 4, alignment: 8
+; X32-NEXT: isImmutable: true,
+; X32: id: [[STACK20:[0-9]+]], type: default, offset: 20, size: 4, alignment: 4
+; X32-NEXT: isImmutable: true,
+; X32: id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 4, alignment: 16
+; X32-NEXT: isImmutable: true,
+; X32: id: [[STACK12:[0-9]+]], type: default, offset: 12, size: 4, alignment: 4
+; X32-NEXT: isImmutable: true,
+; X32: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 4, alignment: 8
+; X32-NEXT: isImmutable: true,
+; X32: id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 4, alignment: 4
+; X32-NEXT: isImmutable: true,
+; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16
+; X32-NEXT: isImmutable: true,
; X32: [[ARG1L_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
; X32-NEXT: [[ARG1L:%[0-9]+]](s32) = G_LOAD [[ARG1L_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
@@ -249,8 +304,10 @@ define float @test_float_args(float %arg
; X64-NEXT: RET 0, implicit %xmm0
; X32: fixedStack:
-; X32: id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 4, alignment: 4, isImmutable: true,
-; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, isImmutable: true,
+; X32: id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 4, alignment: 4,
+; X32-NEXT: isImmutable: true,
+; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16
+; X32-NEXT: isImmutable: true,
; X32: [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
; X32-NEXT: [[ARG1:%[0-9]+]](s32) = G_LOAD [[ARG1_ADDR:%[0-9]+]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
; X32-NEXT: [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
@@ -270,8 +327,12 @@ define double @test_double_args(double %
; X64-NEXT: RET 0, implicit %xmm0
; X32: fixedStack:
-; X32: id: [[STACK4:[0-9]+]], type: default, offset: 8, size: 8, alignment: 8, isImmutable: true,
-; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 8, alignment: 16, isImmutable: true,
+; X32: id: [[STACK4:[0-9]+]], type: default, offset: 8, size: 8, alignment: 8,
+; X32-NEXT: isImmutable: true,
+
+; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 8, alignment: 16,
+; X32-NEXT: isImmutable: true,
+
; X32: [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
; X32-NEXT: [[ARG1:%[0-9]+]](s64) = G_LOAD [[ARG1_ADDR:%[0-9]+]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0)
; X32-NEXT: [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
@@ -322,11 +383,12 @@ define i32 * @test_memop_i32(i32 * %p1)
;X64-NEXT: RET 0, implicit %rax
;X32: fixedStack:
-;X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, isImmutable: true,
+;X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16,
+;X32-NEXT: isImmutable: true,
;X32: %1(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
;X32-NEXT: %0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
;X32-NEXT: %eax = COPY %0(p0)
;X32-NEXT: RET 0, implicit %eax
ret i32 * %p1;
-}
\ No newline at end of file
+}
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