[llvm] r308657 - [X86] Allow masks with more than 6 bits set on the x << (y & mask) optimization for the 64-bit memory shifts.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Thu Jul 20 12:29:58 2017
New Revision: 308657

URL: http://llvm.org/viewvc/llvm-project?rev=308657&view=rev
Log:
[X86] Allow masks with more than 6 bits set on the x << (y & mask) optimization for the 64-bit memory shifts.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrCompiler.td
    llvm/trunk/test/CodeGen/X86/shift-and.ll

Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=308657&r1=308656&r2=308657&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Thu Jul 20 12:29:58 2017
@@ -1654,7 +1654,7 @@ multiclass MaskedShiftAmountPats<SDNode
   // (shift x (and y, 63)) ==> (shift x, y)
   def : Pat<(frag GR64:$src1, (and CL, immShift64)),
             (!cast<Instruction>(name # "64rCL") GR64:$src1)>;
-  def : Pat<(store (frag (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
+  def : Pat<(store (frag (loadi64 addr:$dst), (and CL, immShift64)), addr:$dst),
             (!cast<Instruction>(name # "64mCL") addr:$dst)>;
 }
 

Modified: llvm/trunk/test/CodeGen/X86/shift-and.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shift-and.ll?rev=308657&r1=308656&r2=308657&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/shift-and.ll (original)
+++ llvm/trunk/test/CodeGen/X86/shift-and.ll Thu Jul 20 12:29:58 2017
@@ -99,7 +99,6 @@ define i64 @t5(i64 %t, i64 %val) nounwin
 define void @t5ptr(i64 %t, i64* %ptr) nounwind {
 ; X64-LABEL: t5ptr:
 ; X64:       ## BB#0:
-; X64-NEXT:    andb $-65, %dil
 ; X64-NEXT:    movl %edi, %ecx
 ; X64-NEXT:    shrq %cl, (%rsi)
 ; X64-NEXT:    retq