[llvm] r308590 - [X86] Add test cases for (shift x (and y, (BitWidth-1))) to the BMI2 shift test.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Wed Jul 19 23:19:54 2017
New Revision: 308590

URL: http://llvm.org/viewvc/llvm-project?rev=308590&view=rev
Log:
[X86] Add test cases for (shift x (and y, (BitWidth-1))) to the BMI2 shift test.

We should use SHLX and similar instructions for these patterns, but we currently don't.

Modified:
    llvm/trunk/test/CodeGen/X86/shift-bmi2.ll

Modified: llvm/trunk/test/CodeGen/X86/shift-bmi2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shift-bmi2.ll?rev=308590&r1=308589&r2=308590&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/shift-bmi2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/shift-bmi2.ll Wed Jul 19 23:19:54 2017
@@ -209,3 +209,96 @@ define i64 @ashr64p(i64* %p, i64 %shamt)
   %shl = ashr i64 %x, %shamt
   ret i64 %shl
 }
+
+define i32 @shl32and(i32 %t, i32 %val) nounwind {
+; BMI2-LABEL: shl32and:
+; BMI2:       # BB#0:
+; BMI2-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; BMI2-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; BMI2-NEXT:    shll %cl, %eax
+; BMI2-NEXT:    retl
+;
+; BMI264-LABEL: shl32and:
+; BMI264:       # BB#0:
+; BMI264-NEXT:    movl %edi, %ecx
+; BMI264-NEXT:    shll %cl, %esi
+; BMI264-NEXT:    movl %esi, %eax
+; BMI264-NEXT:    retq
+  %shamt = and i32 %t, 31
+  %res = shl i32 %val, %shamt
+  ret i32 %res
+}
+
+define i64 @shl64and(i64 %t, i64 %val) nounwind {
+; BMI264-LABEL: shl64and:
+; BMI264:       # BB#0:
+; BMI264-NEXT:    movl %edi, %ecx
+; BMI264-NEXT:    shlq %cl, %rsi
+; BMI264-NEXT:    movq %rsi, %rax
+; BMI264-NEXT:    retq
+  %shamt = and i64 %t, 63
+  %res = shl i64 %val, %shamt
+  ret i64 %res
+}
+
+define i32 @lshr32and(i32 %t, i32 %val) nounwind {
+; BMI2-LABEL: lshr32and:
+; BMI2:       # BB#0:
+; BMI2-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; BMI2-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; BMI2-NEXT:    shrl %cl, %eax
+; BMI2-NEXT:    retl
+;
+; BMI264-LABEL: lshr32and:
+; BMI264:       # BB#0:
+; BMI264-NEXT:    movl %edi, %ecx
+; BMI264-NEXT:    shrl %cl, %esi
+; BMI264-NEXT:    movl %esi, %eax
+; BMI264-NEXT:    retq
+  %shamt = and i32 %t, 31
+  %res = lshr i32 %val, %shamt
+  ret i32 %res
+}
+
+define i64 @lshr64and(i64 %t, i64 %val) nounwind {
+; BMI264-LABEL: lshr64and:
+; BMI264:       # BB#0:
+; BMI264-NEXT:    movl %edi, %ecx
+; BMI264-NEXT:    shrq %cl, %rsi
+; BMI264-NEXT:    movq %rsi, %rax
+; BMI264-NEXT:    retq
+  %shamt = and i64 %t, 63
+  %res = lshr i64 %val, %shamt
+  ret i64 %res
+}
+
+define i32 @ashr32and(i32 %t, i32 %val) nounwind {
+; BMI2-LABEL: ashr32and:
+; BMI2:       # BB#0:
+; BMI2-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; BMI2-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; BMI2-NEXT:    sarl %cl, %eax
+; BMI2-NEXT:    retl
+;
+; BMI264-LABEL: ashr32and:
+; BMI264:       # BB#0:
+; BMI264-NEXT:    movl %edi, %ecx
+; BMI264-NEXT:    sarl %cl, %esi
+; BMI264-NEXT:    movl %esi, %eax
+; BMI264-NEXT:    retq
+  %shamt = and i32 %t, 31
+  %res = ashr i32 %val, %shamt
+  ret i32 %res
+}
+
+define i64 @ashr64and(i64 %t, i64 %val) nounwind {
+; BMI264-LABEL: ashr64and:
+; BMI264:       # BB#0:
+; BMI264-NEXT:    movl %edi, %ecx
+; BMI264-NEXT:    sarq %cl, %rsi
+; BMI264-NEXT:    movq %rsi, %rax
+; BMI264-NEXT:    retq
+  %shamt = and i64 %t, 63
+  %res = ashr i64 %val, %shamt
+  ret i64 %res
+}