[PATCH] D35647: [lld] [COFF] Support 128 bit SIMD/FP ldr/str in IMAGE_REL_ARM64_PAGEOFFSET_12L

[Martin Storsjö via Phabricator via llvm-commits]

mstorsjo added a comment.

In https://reviews.llvm.org/D35647#815266, @ruiu wrote:

> Where is this behavior documented?


On page 533 and 1108 in "ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile", at https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile. I found a direct link to a copy if the pdf at http://mazsola.iit.uni-miskolc.hu/~drdani/docs_arm/DDI0487A_e_armv8_arm.pdf as well.

Or if you mean what instruction forms IMAGE_REL_ARM64_PAGEOFFSET_12L can refer to; the official pecoff document doesn't say, but this is based on the instructions that I've seen LLVM produce, with this relocation. That originates from AArch64::fixup_aarch64_ldst_imm12_scale1, ..._scale2, 4, 8 and 16 (in lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp) - I haven't tried to backtrack to see if those can be applied to other instruction forms as well.



================
Comment at: COFF/Chunks.cpp:190
+  // the third bit in Size.
+  if (((Orig >> 26) & 1) != 0) // SIMD/FP
+    Size |= ((Orig >> 23) & 0x01) << 2;
----------------
ruiu wrote:
> This is probably more straightforward:
> 
>   if (Orig & 0x280000)
>     Size += 4;
Sure - I'll update the patch later today.


https://reviews.llvm.org/D35647