[llvm] r308518 - [AArch64] Force relocations for all ADRP instructions
Martin Storsjo via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 19 13:14:32 PDT 2017
Author: mstorsjo
Date: Wed Jul 19 13:14:32 2017
New Revision: 308518
URL: http://llvm.org/viewvc/llvm-project?rev=308518&view=rev
Log:
[AArch64] Force relocations for all ADRP instructions
This generalizes an existing fix from ELF to MachO and COFF.
Test that an ADRP to a local symbol whose offset is known at assembly
time still produces relocations, both for MachO and COFF. Test that
an ADRP without a @page modifier on MachO fails (previously it
didn't).
Differential Revision: https://reviews.llvm.org/D35544
Added:
llvm/trunk/test/MC/AArch64/macho-adrp-missing-reloc.s
llvm/trunk/test/MC/AArch64/macho-adrp-page.s
Modified:
llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
llvm/trunk/test/MC/AArch64/coff-relocations.s
Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp?rev=308518&r1=308517&r2=308518&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp Wed Jul 19 13:14:32 2017
@@ -88,6 +88,9 @@ public:
unsigned getPointerSize() const { return 8; }
unsigned getFixupKindContainereSizeInBytes(unsigned Kind) const;
+
+ bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
+ const MCValue &Target) override;
};
} // end anonymous namespace
@@ -338,6 +341,26 @@ bool AArch64AsmBackend::writeNopData(uin
return true;
}
+bool AArch64AsmBackend::shouldForceRelocation(const MCAssembler &Asm,
+ const MCFixup &Fixup,
+ const MCValue &Target) {
+ // The ADRP instruction adds some multiple of 0x1000 to the current PC &
+ // ~0xfff. This means that the required offset to reach a symbol can vary by
+ // up to one step depending on where the ADRP is in memory. For example:
+ //
+ // ADRP x0, there
+ // there:
+ //
+ // If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and
+ // we'll need that as an offset. At any other address "there" will be in the
+ // same page as the ADRP and the instruction should encode 0x0. Assuming the
+ // section isn't 0x1000-aligned, we therefore need to delegate this decision
+ // to the linker -- a relocation!
+ if ((uint32_t)Fixup.getKind() == AArch64::fixup_aarch64_pcrel_adrp_imm21)
+ return true;
+ return false;
+}
+
namespace {
namespace CU {
@@ -544,31 +567,8 @@ public:
MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
return createAArch64ELFObjectWriter(OS, OSABI, IsLittleEndian, IsILP32);
}
-
- bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
- const MCValue &Target) override;
};
-bool ELFAArch64AsmBackend::shouldForceRelocation(const MCAssembler &Asm,
- const MCFixup &Fixup,
- const MCValue &Target) {
- // The ADRP instruction adds some multiple of 0x1000 to the current PC &
- // ~0xfff. This means that the required offset to reach a symbol can vary by
- // up to one step depending on where the ADRP is in memory. For example:
- //
- // ADRP x0, there
- // there:
- //
- // If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and
- // we'll need that as an offset. At any other address "there" will be in the
- // same page as the ADRP and the instruction should encode 0x0. Assuming the
- // section isn't 0x1000-aligned, we therefore need to delegate this decision
- // to the linker -- a relocation!
- if ((uint32_t)Fixup.getKind() == AArch64::fixup_aarch64_pcrel_adrp_imm21)
- return true;
- return false;
-}
-
}
namespace {
Modified: llvm/trunk/test/MC/AArch64/coff-relocations.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/coff-relocations.s?rev=308518&r1=308517&r2=308518&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/coff-relocations.s (original)
+++ llvm/trunk/test/MC/AArch64/coff-relocations.s Wed Jul 19 13:14:32 2017
@@ -26,6 +26,10 @@ add x0, x0, :lo12:foo
; IMAGE_REL_ARM64_PAGEOFFSET_12L
ldr x0, [x0, :lo12:foo]
+; IMAGE_REL_ARM64_PAGEBASE_REL21, even if the symbol offset is known
+adrp x0, bar
+bar:
+
; IMAGE_REL_ARM64_SECREL
.secrel32 .Linfo_bar
.Linfo_bar:
@@ -33,7 +37,6 @@ ldr x0, [x0, :lo12:foo]
; IMAGE_REL_ARM64_SECTION
.secidx func
-
; CHECK: Format: COFF-ARM64
; CHECK: Arch: aarch64
; CHECK: AddressSize: 64bit
@@ -46,7 +49,8 @@ ldr x0, [x0, :lo12:foo]
; CHECK: 0x18 IMAGE_REL_ARM64_PAGEBASE_REL21 foo
; CHECK: 0x1C IMAGE_REL_ARM64_PAGEOFFSET_12A foo
; CHECK: 0x20 IMAGE_REL_ARM64_PAGEOFFSET_12L foo
-; CHECK: 0x24 IMAGE_REL_ARM64_SECREL .text
-; CHECK: 0x28 IMAGE_REL_ARM64_SECTION func
+; CHECK: 0x24 IMAGE_REL_ARM64_PAGEBASE_REL21 bar
+; CHECK: 0x28 IMAGE_REL_ARM64_SECREL .text
+; CHECK: 0x2C IMAGE_REL_ARM64_SECTION func
; CHECK: }
; CHECK: ]
Added: llvm/trunk/test/MC/AArch64/macho-adrp-missing-reloc.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/macho-adrp-missing-reloc.s?rev=308518&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/macho-adrp-missing-reloc.s (added)
+++ llvm/trunk/test/MC/AArch64/macho-adrp-missing-reloc.s Wed Jul 19 13:14:32 2017
@@ -0,0 +1,6 @@
+; RUN: not llvm-mc < %s -triple arm64-apple-darwin -filetype=obj -o - 2>&1 | FileCheck %s
+
+; CHECK: error: ADR/ADRP relocations must be GOT relative
+ adrp x3, Lbar
+Lbar:
+ ret
Added: llvm/trunk/test/MC/AArch64/macho-adrp-page.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/macho-adrp-page.s?rev=308518&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/macho-adrp-page.s (added)
+++ llvm/trunk/test/MC/AArch64/macho-adrp-page.s Wed Jul 19 13:14:32 2017
@@ -0,0 +1,6 @@
+; RUN: llvm-mc < %s -triple arm64-apple-darwin -filetype=obj -o - | llvm-readobj -r - | FileCheck %s
+
+ adrp x3, Lbar at page
+; CHECK: ARM64_RELOC_PAGE21
+Lbar:
+ ret
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