[llvm] r308510 - [Hexagon] Fix a bug in r308502: post-inc offset is always 0
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 19 12:17:32 PDT 2017
Author: kparzysz
Date: Wed Jul 19 12:17:32 2017
New Revision: 308510
URL: http://llvm.org/viewvc/llvm-project?rev=308510&view=rev
Log:
[Hexagon] Fix a bug in r308502: post-inc offset is always 0
Added:
llvm/trunk/test/CodeGen/Hexagon/postinc-baseoffset.mir
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=308510&r1=308509&r2=308510&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Wed Jul 19 12:17:32 2017
@@ -1715,8 +1715,8 @@ bool HexagonInstrInfo::areMemAccessesTri
if (!MIa.getOperand(OffsetPosA).isImm() ||
!MIb.getOperand(OffsetPosB).isImm())
return false;
- int OffsetA = OffA.getImm();
- int OffsetB = OffB.getImm();
+ int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
+ int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
// This is a mem access with the same base register and known offsets from it.
// Reason about it.
Added: llvm/trunk/test/CodeGen/Hexagon/postinc-baseoffset.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/postinc-baseoffset.mir?rev=308510&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/postinc-baseoffset.mir (added)
+++ llvm/trunk/test/CodeGen/Hexagon/postinc-baseoffset.mir Wed Jul 19 12:17:32 2017
@@ -0,0 +1,22 @@
+# RUN: llc -march=hexagon -start-before hexagon-packetizer %s -o - | FileCheck %s
+
+# Check that we don't packetize these two instructions together. It happened
+# earlier because "offset" in the post-increment instruction was taken to be 8.
+
+# CHECK: memw(r0+#0) = #-1
+# CHECK: }
+# CHECK: {
+# CHECK: r1 = memw(r0++#8)
+
+--- |
+ define void @fred(i32* %a) { ret void }
+...
+---
+name: fred
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: %r0
+ S4_storeiri_io %r0, 0, -1 :: (store 4 into %ir.a)
+ %r1, %r0 = L2_loadri_pi %r0, 8 :: (load 4 from %ir.a)
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