[llvm] r308278 - GlobalISel: Support G_(S|U)REM widening in LegalizerHelper

[Diana Picus via llvm-commits]

Author: rovka
Date: Tue Jul 18 02:08:47 2017
New Revision: 308278

URL: http://llvm.org/viewvc/llvm-project?rev=308278&view=rev
Log:
GlobalISel: Support G_(S|U)REM widening in LegalizerHelper

Treat widening G_SREM and G_UREM the same as G_SDIV and G_UDIV. This is
going to be used in the ARM backend (and that's when the test will come
too).

Modified:
    llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp?rev=308278&r1=308277&r2=308278&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Tue Jul 18 02:08:47 2017
@@ -433,9 +433,12 @@ LegalizerHelper::widenScalar(MachineInst
   }
   case TargetOpcode::G_SDIV:
   case TargetOpcode::G_UDIV:
+  case TargetOpcode::G_SREM:
+  case TargetOpcode::G_UREM:
   case TargetOpcode::G_ASHR:
   case TargetOpcode::G_LSHR: {
     unsigned ExtOp = MI.getOpcode() == TargetOpcode::G_SDIV ||
+                             MI.getOpcode() == TargetOpcode::G_SREM ||
                              MI.getOpcode() == TargetOpcode::G_ASHR
                          ? TargetOpcode::G_SEXT
                          : TargetOpcode::G_ZEXT;