[polly] r308215 - [ScopInfo] Simplify new access functions under domain context
Tobias Grosser via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 17 13:47:10 PDT 2017
Author: grosser
Date: Mon Jul 17 13:47:10 2017
New Revision: 308215
URL: http://llvm.org/viewvc/llvm-project?rev=308215&view=rev
Log:
[ScopInfo] Simplify new access functions under domain context
Summary:
We do not keep domain constraints on access functions when building the
scop. Hence, for consistency reasons, it makes also sense to not include
them when storing a new access function. This change results in simpler
access functions that make output easier to read.
This patch also helps to make DeLICMed memory accesses to be understood by
our matrix multiplication pattern matching pass. Further changes to the
matrix multiplication pattern matching are needed for this to work, so the
corresponding test case will be added in a future commit.
Reviewers: Meinersbur, bollu, gareevroman, efriedma, huihuiz, sebpop, simbuerg
Subscribers: pollydev, llvm-commits
Tags: #polly
Differential Revision: https://reviews.llvm.org/D35237
Modified:
polly/trunk/lib/Analysis/ScopInfo.cpp
polly/trunk/test/DeLICM/reduction.ll
polly/trunk/test/DeLICM/reduction_constant_selfconflict.ll
polly/trunk/test/DeLICM/reduction_looprotate_gvnpre.ll
polly/trunk/test/DeLICM/reduction_looprotate_hoisted.ll
polly/trunk/test/DeLICM/reduction_looprotate_licm.ll
polly/trunk/test/DeLICM/reduction_looprotate_load.ll
polly/trunk/test/DeLICM/reduction_looprotate_readonly.ll
polly/trunk/test/DeLICM/reduction_looprotate_synthesizable.ll
polly/trunk/test/DeLICM/reduction_looprotate_undef.ll
polly/trunk/test/DeLICM/reduction_overapproximate.ll
polly/trunk/test/DeLICM/reduction_preheader.ll
polly/trunk/test/Isl/CodeGen/MemAccess/map_scalar_access.ll
polly/trunk/test/ScheduleOptimizer/mat_mul_pattern_data_layout.ll
Modified: polly/trunk/lib/Analysis/ScopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=308215&r1=308214&r2=308215&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/ScopInfo.cpp (original)
+++ polly/trunk/lib/Analysis/ScopInfo.cpp Mon Jul 17 13:47:10 2017
@@ -1240,6 +1240,7 @@ void MemoryAccess::setNewAccessRelation(
#endif
isl_map_free(NewAccessRelation);
+ NewAccess = isl_map_gist_domain(NewAccess, getStatement()->getDomain());
NewAccessRelation = NewAccess;
}
Modified: polly/trunk/test/DeLICM/reduction.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/DeLICM/reduction.ll?rev=308215&r1=308214&r2=308215&view=diff
==============================================================================
--- polly/trunk/test/DeLICM/reduction.ll (original)
+++ polly/trunk/test/DeLICM/reduction.ll Mon Jul 17 13:47:10 2017
@@ -60,32 +60,32 @@ return:
; CHECK-NEXT: Stmt_outer_for
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_outer_for[i0] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_outer_for[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; CHECK-NEXT: new: { Stmt_outer_for[i0] -> MemRef_A[i0] : i0 <= 1 };
; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 4 };
+; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 4 };
+; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_body
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
-; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
-; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_exit
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: }
Modified: polly/trunk/test/DeLICM/reduction_constant_selfconflict.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/DeLICM/reduction_constant_selfconflict.ll?rev=308215&r1=308214&r2=308215&view=diff
==============================================================================
--- polly/trunk/test/DeLICM/reduction_constant_selfconflict.ll (original)
+++ polly/trunk/test/DeLICM/reduction_constant_selfconflict.ll Mon Jul 17 13:47:10 2017
@@ -69,34 +69,34 @@ return:
; CHECK-NEXT: Stmt_reduction_preheader
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 4 };
+; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 4 };
+; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_body
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
-; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and i1 >= 0 and -5i0 <= i1 <= 8 - 5i0 and i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
-; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : i1 >= 0 and -5i0 <= i1 <= 7 - 5i0 and i1 <= 3; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
+; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : i1 <= 7 - 5i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and i1 >= 0 and -5i0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_exit
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: }
Modified: polly/trunk/test/DeLICM/reduction_looprotate_gvnpre.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/DeLICM/reduction_looprotate_gvnpre.ll?rev=308215&r1=308214&r2=308215&view=diff
==============================================================================
--- polly/trunk/test/DeLICM/reduction_looprotate_gvnpre.ll (original)
+++ polly/trunk/test/DeLICM/reduction_looprotate_gvnpre.ll Mon Jul 17 13:47:10 2017
@@ -68,30 +68,30 @@ return:
; CHECK-NEXT: Stmt_reduction_preheader
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_body
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
-; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 and 3i1 <= 22 - 13i0 };
+; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : i0 >= 0 and 0 <= i1 <= 3 and 3i1 <= 21 - 13i0; Stmt_body[1, 3] -> MemRef_A[1] };
+; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 3i1 <= 21 - 13i0; Stmt_body[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
-; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : i0 >= 0 and 0 <= i1 <= 3 and 3i1 <= 21 - 13i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
+; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 3i1 <= 21 - 13i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: }
@@ -99,28 +99,28 @@ return:
; PARTIAL-NEXT: Stmt_reduction_preheader
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
-; PARTIAL-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; PARTIAL-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; PARTIAL-NEXT: Stmt_reduction_for
; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
-; PARTIAL-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; PARTIAL-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
-; PARTIAL-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; PARTIAL-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; PARTIAL-NEXT: Stmt_body
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
-; PARTIAL-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 and 3i1 <= 22 - 13i0 };
+; PARTIAL-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
-; PARTIAL-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : i0 >= 0 and 0 <= i1 <= 3 and 3i1 <= 21 - 13i0; Stmt_body[1, 3] -> MemRef_A[1] };
+; PARTIAL-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 3i1 <= 21 - 13i0; Stmt_body[1, 3] -> MemRef_A[1] };
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; PARTIAL-NEXT: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; PARTIAL-NEXT: Stmt_reduction_inc
; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
-; PARTIAL-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : i0 >= 0 and 0 <= i1 <= 3 and 3i1 <= 21 - 13i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
+; PARTIAL-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 3i1 <= 21 - 13i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
-; PARTIAL-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 2 and 3i1 >= -13i0 };
+; PARTIAL-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : i1 <= 2 };
; PARTIAL-NEXT: }
Modified: polly/trunk/test/DeLICM/reduction_looprotate_hoisted.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/DeLICM/reduction_looprotate_hoisted.ll?rev=308215&r1=308214&r2=308215&view=diff
==============================================================================
--- polly/trunk/test/DeLICM/reduction_looprotate_hoisted.ll (original)
+++ polly/trunk/test/DeLICM/reduction_looprotate_hoisted.ll Mon Jul 17 13:47:10 2017
@@ -70,32 +70,32 @@ return:
; CHECK-NEXT: Stmt_reduction_preheader
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: [Start] -> { Stmt_reduction_preheader[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; CHECK-NEXT: new: [Start] -> { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: [Start] -> { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and -i0 < i1 <= 3 - Start; Stmt_reduction_for[1, 0] -> MemRef_A[1] : Start >= 4; Stmt_reduction_for[0, 0] -> MemRef_A[0] };
+; CHECK-NEXT: new: [Start] -> { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : -i0 < i1 <= 3 - Start; Stmt_reduction_for[1, 0] -> MemRef_A[1] : Start >= 4; Stmt_reduction_for[0, 0] -> MemRef_A[0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: [Start] -> { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and i0 <= i1 <= 3 - Start; Stmt_reduction_for[i0, 0] -> MemRef_A[i0] : 0 <= i0 <= 1 and i0 <= -4 + Start; Stmt_reduction_for[1, 0] -> MemRef_A[1] : Start <= 4 };
+; CHECK-NEXT: new: [Start] -> { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : i0 <= i1 <= 3 - Start; Stmt_reduction_for[i0, 0] -> MemRef_A[i0] : i0 <= -4 + Start; Stmt_reduction_for[1, 0] -> MemRef_A[1] : Start <= 4 }
; CHECK-NEXT: Stmt_body
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_body[i0, i1] -> MemRef_mul[] };
-; CHECK-NEXT: new: [Start] -> { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and i0 <= i1 <= 3 - Start; Stmt_body[i0, 0] -> MemRef_A[i0] : 0 <= i0 <= 1 and i0 <= -4 + Start; Stmt_body[1, 0] -> MemRef_A[1] : Start <= 4 };
+; CHECK-NEXT: new: [Start] -> { Stmt_body[i0, i1] -> MemRef_A[i0] : i0 <= i1 <= 3 - Start; Stmt_body[i0, 0] -> MemRef_A[i0] : i0 <= -4 + Start; Stmt_body[1, 0] -> MemRef_A[1] : Start <= 4 }
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_body[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: [Start] -> { Stmt_body[i0, i1] -> MemRef_A[i0] : Start <= 3 and 0 <= i0 <= 1 and i0 <= i1 <= 3 - Start; Stmt_body[1, 0] -> MemRef_A[1]; Stmt_body[0, 0] -> MemRef_A[0] : Start >= 4 };
+; CHECK-NEXT: new: [Start] -> { Stmt_body[i0, i1] -> MemRef_A[i0] : i0 <= i1 <= 3 - Start; Stmt_body[1, 0] -> MemRef_A[1]; Stmt_body[0, 0] -> MemRef_A[0] : Start >= 4 };
; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_reduction_inc[i0, i1] -> MemRef_mul[] };
-; CHECK-NEXT: new: [Start] -> { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : Start <= 3 and 0 <= i0 <= 1 and i0 <= i1 <= 3 - Start; Stmt_reduction_inc[1, 0] -> MemRef_A[1]; Stmt_reduction_inc[0, 0] -> MemRef_A[0] : Start >= 4 };
+; CHECK-NEXT: new: [Start] -> { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : i0 <= i1 <= 3 - Start; Stmt_reduction_inc[1, 0] -> MemRef_A[1]; Stmt_reduction_inc[0, 0] -> MemRef_A[0] : Start >= 4 };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: [Start] -> { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 < i1 <= 3 - Start; Stmt_reduction_inc[i0, 0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; CHECK-NEXT: new: [Start] -> { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 < i1 <= 3 - Start; Stmt_reduction_inc[i0, 0] -> MemRef_A[i0] }
; CHECK-NEXT: Stmt_reduction_exit
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: [Start] -> { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: [Start] -> { Stmt_reduction_exit[i0] -> MemRef_mul[] };
-; CHECK-NEXT: new: [Start] -> { Stmt_reduction_exit[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; CHECK-NEXT: new: [Start] -> { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: }
Modified: polly/trunk/test/DeLICM/reduction_looprotate_licm.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/DeLICM/reduction_looprotate_licm.ll?rev=308215&r1=308214&r2=308215&view=diff
==============================================================================
--- polly/trunk/test/DeLICM/reduction_looprotate_licm.ll (original)
+++ polly/trunk/test/DeLICM/reduction_looprotate_licm.ll Mon Jul 17 13:47:10 2017
@@ -69,32 +69,32 @@ return:
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_body
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
-; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i1 <= 3 and -14i0 <= 3i1 <= 22 - 14i0; Stmt_body[1, 3] -> MemRef_A[1] };
+; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 3i1 <= 22 - 14i0; Stmt_body[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
-; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i1 <= 3 and -14i0 <= 3i1 <= 22 - 14i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
+; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 3i1 <= 22 - 14i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_exit
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_add[] };
-; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: }
Modified: polly/trunk/test/DeLICM/reduction_looprotate_load.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/DeLICM/reduction_looprotate_load.ll?rev=308215&r1=308214&r2=308215&view=diff
==============================================================================
--- polly/trunk/test/DeLICM/reduction_looprotate_load.ll (original)
+++ polly/trunk/test/DeLICM/reduction_looprotate_load.ll Mon Jul 17 13:47:10 2017
@@ -68,32 +68,32 @@ return:
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_StartPtr[0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_body
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
-; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i1 <= 3 and -14i0 <= 3i1 <= 22 - 14i0; Stmt_body[1, 3] -> MemRef_A[1] };
+; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 3i1 <= 22 - 14i0; Stmt_body[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
-; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i1 <= 3 and -14i0 <= 3i1 <= 22 - 14i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
+; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 3i1 <= 22 - 14i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_exit
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_add[] };
-; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: }
Modified: polly/trunk/test/DeLICM/reduction_looprotate_readonly.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/DeLICM/reduction_looprotate_readonly.ll?rev=308215&r1=308214&r2=308215&view=diff
==============================================================================
--- polly/trunk/test/DeLICM/reduction_looprotate_readonly.ll (original)
+++ polly/trunk/test/DeLICM/reduction_looprotate_readonly.ll Mon Jul 17 13:47:10 2017
@@ -67,32 +67,32 @@ return:
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_Start[] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_body
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
-; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i1 <= 3 and -14i0 <= 3i1 <= 22 - 14i0; Stmt_body[1, 3] -> MemRef_A[1] };
+; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 3i1 <= 22 - 14i0; Stmt_body[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
-; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i1 <= 3 and -14i0 <= 3i1 <= 22 - 14i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
+; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 3i1 <= 22 - 14i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_exit
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_add[] };
-; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: }
Modified: polly/trunk/test/DeLICM/reduction_looprotate_synthesizable.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/DeLICM/reduction_looprotate_synthesizable.ll?rev=308215&r1=308214&r2=308215&view=diff
==============================================================================
--- polly/trunk/test/DeLICM/reduction_looprotate_synthesizable.ll (original)
+++ polly/trunk/test/DeLICM/reduction_looprotate_synthesizable.ll Mon Jul 17 13:47:10 2017
@@ -66,32 +66,32 @@ return:
; CHECK-NEXT: Stmt_reduction_preheader
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_body
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_mul[] };
-; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i1 <= 3 and -14i0 <= 3i1 <= 22 - 14i0; Stmt_body[1, 3] -> MemRef_A[1] };
+; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 3i1 <= 22 - 14i0; Stmt_body[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_mul[] };
-; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i1 <= 3 and -14i0 <= 3i1 <= 22 - 14i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
+; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 3i1 <= 22 - 14i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_exit
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_mul[] };
-; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: }
Modified: polly/trunk/test/DeLICM/reduction_looprotate_undef.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/DeLICM/reduction_looprotate_undef.ll?rev=308215&r1=308214&r2=308215&view=diff
==============================================================================
--- polly/trunk/test/DeLICM/reduction_looprotate_undef.ll (original)
+++ polly/trunk/test/DeLICM/reduction_looprotate_undef.ll Mon Jul 17 13:47:10 2017
@@ -67,32 +67,32 @@ return:
; CHECK-NEXT: Stmt_reduction_preheader
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_body
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_conv[] };
-; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i1 <= 3 and -14i0 <= 3i1 <= 22 - 14i0; Stmt_body[1, 3] -> MemRef_A[1] };
+; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 3i1 <= 22 - 14i0; Stmt_body[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_conv[] };
-; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i1 <= 3 and -14i0 <= 3i1 <= 22 - 14i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
+; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 3i1 <= 22 - 14i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_exit
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_conv[] };
-; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: }
Modified: polly/trunk/test/DeLICM/reduction_overapproximate.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/DeLICM/reduction_overapproximate.ll?rev=308215&r1=308214&r2=308215&view=diff
==============================================================================
--- polly/trunk/test/DeLICM/reduction_overapproximate.ll (original)
+++ polly/trunk/test/DeLICM/reduction_overapproximate.ll Mon Jul 17 13:47:10 2017
@@ -75,39 +75,39 @@ return:
; APPROX-NEXT: Stmt_reduction_checkloop
; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; APPROX-NEXT: { Stmt_reduction_checkloop[i0] -> MemRef_val__phi[] };
-; APPROX-NEXT: new: { Stmt_reduction_checkloop[i0] -> MemRef_A[-1 + i0] : 0 <= i0 <= 3 };
+; APPROX-NEXT: new: { Stmt_reduction_checkloop[i0] -> MemRef_A[-1 + i0] };
; APPROX-NEXT: Stmt_reduction_preheader
; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; APPROX-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
-; APPROX-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[-1 + i0] : 2 <= i0 <= 3 };
+; APPROX-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[-1 + i0] };
; APPROX-NEXT: Stmt_reduction_for
; APPROX-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; APPROX-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
-; APPROX-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and i1 >= 0 and 2 - 3i0 <= i1 <= 11 - 3i0 and i1 <= 2 and i1 <= -2 + i0 };
+; APPROX-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[-1 + i0] };
; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; APPROX-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
-; APPROX-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and i1 >= 0 and 2 - 3i0 <= i1 <= 11 - 3i0 and i1 <= 2 and i1 <= -2 + i0 };
+; APPROX-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[-1 + i0] };
; APPROX-NEXT: Stmt_body
; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; APPROX-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
-; APPROX-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and i1 >= 0 and 2 - 3i0 <= i1 <= 10 - 3i0 and i1 <= 1 and i1 <= -2 + i0 };
+; APPROX-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[-1 + i0] };
; APPROX-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; APPROX-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
-; APPROX-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and 0 <= i1 <= -2 + i0 };
+; APPROX-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[-1 + i0] };
; APPROX-NEXT: Stmt_reduction_inc
; APPROX-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; APPROX-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
-; APPROX-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and 0 <= i1 <= -2 + i0 };
+; APPROX-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[-1 + i0] };
; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; APPROX-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
-; APPROX-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[2] : i0 <= 3 and 0 <= i1 <= -2 + i0 };
+; APPROX-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[2] };
; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; APPROX-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_val__phi[] };
-; APPROX-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and 0 <= i1 <= -2 + i0 };
+; APPROX-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[-1 + i0] };
; APPROX-NEXT: Stmt_reduction_exit
; APPROX-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; APPROX-NEXT: { Stmt_reduction_exit[i0] -> MemRef_val__phi[] };
-; APPROX-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[-1 + i0] : 0 <= i0 <= 3 };
+; APPROX-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[-1 + i0] };
; APPROX-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; APPROX-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[-1 + i0] };
; APPROX-NEXT: }
@@ -120,39 +120,39 @@ return:
; PARTIAL-NEXT: Stmt_reduction_checkloop
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_checkloop[i0] -> MemRef_val__phi[] };
-; PARTIAL-NEXT: new: { Stmt_reduction_checkloop[i0] -> MemRef_A[-1 + i0] : 0 <= i0 <= 1 };
+; PARTIAL-NEXT: new: { Stmt_reduction_checkloop[i0] -> MemRef_A[-1 + i0] : i0 <= 1 };
; PARTIAL-NEXT: Stmt_reduction_preheader
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
-; PARTIAL-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[-1 + i0] : 2 <= i0 <= 3 };
+; PARTIAL-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[-1 + i0] };
; PARTIAL-NEXT: Stmt_reduction_for
; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
-; PARTIAL-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and i1 >= 0 and 2 - 3i0 <= i1 <= 11 - 3i0 and i1 <= 2 and i1 <= -2 + i0 };
+; PARTIAL-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[-1 + i0] };
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
-; PARTIAL-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and i1 >= 0 and 2 - 3i0 <= i1 <= 11 - 3i0 and i1 <= 2 and i1 <= -2 + i0 };
+; PARTIAL-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[-1 + i0] };
; PARTIAL-NEXT: Stmt_body
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
-; PARTIAL-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and i1 >= 0 and 2 - 3i0 <= i1 <= 10 - 3i0 and i1 <= 1 and i1 <= -2 + i0 };
+; PARTIAL-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[-1 + i0] };
; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
-; PARTIAL-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and 0 <= i1 <= -2 + i0 };
+; PARTIAL-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[-1 + i0] };
; PARTIAL-NEXT: Stmt_reduction_inc
; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
-; PARTIAL-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[-1 + i0] : i0 <= 3 and 0 <= i1 <= -2 + i0 };
+; PARTIAL-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[-1 + i0] };
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
; PARTIAL-NEXT: new: { Stmt_reduction_inc[3, 0] -> MemRef_A[2] };
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_val__phi[] };
-; PARTIAL-NEXT: new: { Stmt_reduction_inc[i0, -2 + i0] -> MemRef_A[-1 + i0] : 2 <= i0 <= 3 };
+; PARTIAL-NEXT: new: { Stmt_reduction_inc[i0, -2 + i0] -> MemRef_A[-1 + i0] };
; PARTIAL-NEXT: Stmt_reduction_exit
; PARTIAL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; PARTIAL-NEXT: { Stmt_reduction_exit[i0] -> MemRef_val__phi[] };
-; PARTIAL-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[-1 + i0] : 0 <= i0 <= 3 };
+; PARTIAL-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[-1 + i0] };
; PARTIAL-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; PARTIAL-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[-1 + i0] };
; PARTIAL-NEXT: }
Modified: polly/trunk/test/DeLICM/reduction_preheader.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/DeLICM/reduction_preheader.ll?rev=308215&r1=308214&r2=308215&view=diff
==============================================================================
--- polly/trunk/test/DeLICM/reduction_preheader.ll (original)
+++ polly/trunk/test/DeLICM/reduction_preheader.ll Mon Jul 17 13:47:10 2017
@@ -98,33 +98,33 @@ return:
; CHECK-NEXT: Stmt_reduction_preheader
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_preheader[i0] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; CHECK-NEXT: new: { Stmt_reduction_preheader[i0] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_for
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 4 };
+; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 4 };
+; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_body
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
-; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and 0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and i1 >= 0 and -5i0 <= i1 <= 8 - 5i0 and i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
-; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : i1 >= 0 and -5i0 <= i1 <= 7 - 5i0 and i1 <= 3; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
+; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : i1 <= 7 - 5i0; Stmt_reduction_inc[1, 3] -> MemRef_A[1] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] : 0 <= i0 <= 1 and i1 >= 0 and -5i0 <= i1 <= 3 };
+; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
; CHECK-NEXT: Stmt_reduction_exit
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] : 0 <= i0 <= 1 };
+; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
; CHECK-NEXT: }
Modified: polly/trunk/test/Isl/CodeGen/MemAccess/map_scalar_access.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/Isl/CodeGen/MemAccess/map_scalar_access.ll?rev=308215&r1=308214&r2=308215&view=diff
==============================================================================
--- polly/trunk/test/Isl/CodeGen/MemAccess/map_scalar_access.ll (original)
+++ polly/trunk/test/Isl/CodeGen/MemAccess/map_scalar_access.ll Mon Jul 17 13:47:10 2017
@@ -66,10 +66,10 @@ return:
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> [0, 1, i1, 0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
+; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_for[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[i0] };
+; CHECK-NEXT: new: { Stmt_reduction_for[i0, i1] -> MemRef_A[0] };
; CHECK-NEXT: Stmt_body
; CHECK-NEXT: Domain :=
; CHECK-NEXT: { Stmt_body[0, i1] : 0 <= i1 <= 3 };
@@ -77,10 +77,10 @@ return:
; CHECK-NEXT: { Stmt_body[i0, i1] -> [0, 1, i1, 1] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_add[] };
-; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
+; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_body[i0, i1] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[i0] };
+; CHECK-NEXT: new: { Stmt_body[i0, i1] -> MemRef_A[0] };
; CHECK-NEXT: Stmt_reduction_inc
; CHECK-NEXT: Domain :=
; CHECK-NEXT: { Stmt_reduction_inc[0, i1] : 0 <= i1 <= 3 };
@@ -88,10 +88,10 @@ return:
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> [0, 1, i1, 2] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_add[] };
-; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
+; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_inc[i0, i1] -> MemRef_phi__phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[i0] };
+; CHECK-NEXT: new: { Stmt_reduction_inc[i0, i1] -> MemRef_A[0] };
; CHECK-NEXT: Stmt_reduction_exit
; CHECK-NEXT: Domain :=
; CHECK-NEXT: { Stmt_reduction_exit[0] };
@@ -99,10 +99,10 @@ return:
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> [0, 2, 0, 0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_A[0] };
-; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
+; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[0] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_reduction_exit[i0] -> MemRef_phi[] };
-; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[i0] };
+; CHECK-NEXT: new: { Stmt_reduction_exit[i0] -> MemRef_A[0] };
; CHECK-NEXT: }
; CHECK: New access function '{ Stmt_outer_for[i0] -> MemRef_A[i0] }' detected in JSCOP file
; CHECK-NEXT: New access function '{ Stmt_reduction_for[i0, i1] -> MemRef_A[i0] }' detected in JSCOP file
Modified: polly/trunk/test/ScheduleOptimizer/mat_mul_pattern_data_layout.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScheduleOptimizer/mat_mul_pattern_data_layout.ll?rev=308215&r1=308214&r2=308215&view=diff
==============================================================================
--- polly/trunk/test/ScheduleOptimizer/mat_mul_pattern_data_layout.ll (original)
+++ polly/trunk/test/ScheduleOptimizer/mat_mul_pattern_data_layout.ll Mon Jul 17 13:47:10 2017
@@ -22,10 +22,10 @@
; CHECK-NEXT: double Packed_A[ { [] -> [(24)] } ][ { [] -> [(256)] } ][ { [] -> [(4)] } ]; // Element size 8
;
; CHECK: { Stmt_Copy_0[i0, i1, i2] -> MemRef_arg6[i0, i2] };
-; CHECK-NEXT: new: { Stmt_Copy_0[i0, i1, i2] -> Packed_A[o0, o1, o2] : 256*floor((-i2 + o1)/256) = -i2 + o1 and 4*floor((-i0 + o2)/4) = -i0 + o2 and 0 <= o1 <= 255 and 0 <= o2 <= 3 and -3 + i0 - 4o0 <= 96*floor((i0)/96) <= i0 - 4o0 };
+; CHECK-NEXT: new: { Stmt_Copy_0[i0, i1, i2] -> Packed_A[o0, o1, o2] : 256*floor((-i2 + o1)/256) = -i2 + o1 and 96*floor((-i0 + 4o0 + o2)/96) = -i0 + 4o0 + o2 and 0 <= o1 <= 255 and o2 >= 0 and -4o0 <= o2 <= 95 - 4o0 and o2 <= 3 };
;
; CHECK: { Stmt_Copy_0[i0, i1, i2] -> MemRef_arg7[i2, i1] };
-; CHECK-NEXT: new: { Stmt_Copy_0[i0, i1, i2] -> Packed_B[o0, o1, o2] : 256*floor((-i2 + o1)/256) = -i2 + o1 and 8*floor((-i1 + o2)/8) = -i1 + o2 and 0 <= o1 <= 255 and 0 <= o2 <= 7 and -7 + i1 - 8o0 <= 2048*floor((i1)/2048) <= i1 - 8o0 };
+; CHECK-NEXT: new: { Stmt_Copy_0[i0, i1, i2] -> Packed_B[o0, o1, i1 - 8o0] : 256*floor((-i2 + o1)/256) = -i2 + o1 and -7 + i1 <= 8o0 <= i1 and 0 <= o1 <= 255 };
;
; CHECK: CopyStmt_0
; CHECK-NEXT: Domain :=
@@ -34,7 +34,7 @@
; CHECK-NEXT: ;
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: null;
-; CHECK-NEXT: new: { CopyStmt_0[i0, i1, i2] -> Packed_B[o0, o1, o2] : 256*floor((-i2 + o1)/256) = -i2 + o1 and 8*floor((-i1 + o2)/8) = -i1 + o2 and 0 <= o1 <= 255 and 0 <= o2 <= 7 and -7 + i1 - 8o0 <= 2048*floor((i1)/2048) <= i1 - 8o0 };
+; CHECK-NEXT: new: { CopyStmt_0[i0, i1, i2] -> Packed_B[o0, o1, i1 - 8o0] : 256*floor((-i2 + o1)/256) = -i2 + o1 and -7 + i1 <= 8o0 <= i1 and 0 <= o1 <= 255 };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: null;
; CHECK-NEXT: new: { CopyStmt_0[i0, i1, i2] -> MemRef_arg7[i2, i1] };
@@ -45,7 +45,7 @@
; CHECK-NEXT: ;
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: null;
-; CHECK-NEXT: new: { CopyStmt_1[i0, i1, i2] -> Packed_A[o0, o1, o2] : 256*floor((-i2 + o1)/256) = -i2 + o1 and 4*floor((-i0 + o2)/4) = -i0 + o2 and 0 <= o1 <= 255 and 0 <= o2 <= 3 and -3 + i0 - 4o0 <= 96*floor((i0)/96) <= i0 - 4o0 };
+; CHECK-NEXT: new: { CopyStmt_1[i0, i1, i2] -> Packed_A[o0, o1, o2] : 256*floor((-i2 + o1)/256) = -i2 + o1 and 96*floor((-i0 + 4o0 + o2)/96) = -i0 + 4o0 + o2 and 0 <= o1 <= 255 and o2 >= 0 and -4o0 <= o2 <= 95 - 4o0 and o2 <= 3 };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: null;
; CHECK-NEXT: new: { CopyStmt_1[i0, i1, i2] -> MemRef_arg6[i0, i2] };
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