[PATCH] D34661: [X86][MMX] Added custom lowering action for MMX SELECT (PR30418)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

Code now looks fine, just some further tidying up of the test cases



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Comment at: test/CodeGen/X86/select-mmx.ll:2
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+mmx < %s | FileCheck %s --check-prefix=X64
+; RUN: llc -mtriple=i686-unknown-unknown -mattr=+mmx < %s | FileCheck %s --check-prefix=I32
+
----------------
You should regenerate the codegen with utils/update_llc_test_checks.py


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Comment at: test/CodeGen/X86/select-mmx.ll:12
+
+define i64 @test47(i64 %arg) local_unnamed_addr #1 {
+;
----------------
You can drop 'local_unnamed_addr #1' and probably add 'nonuwind' instead


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Comment at: test/CodeGen/X86/select-mmx.ll:49
+  %slct = select i1 %cond, x86_mmx bitcast (i64 7 to x86_mmx), x86_mmx bitcast (i64 0 to x86_mmx)
+  %psll = tail call x86_mmx @llvm.x86.mmx.psll.w(x86_mmx %slct, x86_mmx %slct) #3
+  %retc = bitcast x86_mmx %psll to i64
----------------
Remove the #3


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Comment at: test/CodeGen/X86/select-mmx.ll:62
+
+define i64 @test49(i64 %arg, i64 %x, i64 %y) local_unnamed_addr #1 {
+;
----------------
You can drop 'local_unnamed_addr #1' and probably add 'nonuwind' instead


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Comment at: test/CodeGen/X86/select-mmx.ll:97
+  %slct = select i1 %cond, x86_mmx %xmmx, x86_mmx %ymmx
+  %psll = tail call x86_mmx @llvm.x86.mmx.psll.w(x86_mmx %slct, x86_mmx %slct) #3
+  %retc = bitcast x86_mmx %psll to i64
----------------
Remove the #3


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Comment at: test/CodeGen/X86/select-mmx.ll:102
+
+declare x86_mmx @llvm.x86.mmx.psll.w(x86_mmx, x86_mmx) #2
+
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Remove the #2


https://reviews.llvm.org/D34661