[PATCH] D35010: [IRCE] Recognize loops with ne/eq latch conditions

[Sanjoy Das via Phabricator via llvm-commits]

sanjoy requested changes to this revision.
sanjoy added a comment.
This revision now requires changes to proceed.

Some comments / questions inline.



================
Comment at: lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp:818
+      // while (true) {               while (true) {
+      //   if (++i == len)     --->     if (++i > len - 1)
+      //     break;                       break;
----------------
I'm not sure why you need to handle this case differently than the above.  That is,

```
while (true) {
  if (++i == len)
    break;
}
```

seems equivalent to

```
while (++i != len) {
}
```



================
Comment at: lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp:853
+      // it virtually when we replaced EQ with SGT.
+      if (!DecreasedRightValueByOne) {
+        IRBuilder<> B(Preheader->getTerminator());
----------------
I'm missing a link here.  IIUC:

 - You started with the backedge taken condition as `!(++i == len)`
 - `!(++i == len)` is equivalent to `!(++i >s (len - 1))`, after checking `len - 1` does not overflow (this is the new step you added)
 - `!(++i >s (len - 1))` is equivalent to `(++i s<= (len - 1))`
 - `(++i s<= (len - 1))` is equivalent to `(++i s< len)` after checking that `(len - 1) + 1` does not overflow

Where does `DecreasedRightValueByOne` come in?


https://reviews.llvm.org/D35010