[PATCH] D35260: [AArch64] Move AES instruction fusion support

[Florian Hahn via Phabricator via llvm-commits]

fhahn added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64SchedM1.td:637
 def : InstRW<[M1WriteVSTC,
-              WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
+              WriteAdr],      (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
 
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This is an unrelated whitespace change?


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Comment at: llvm/test/CodeGen/AArch64/misched-fusion-aes.ll:100
 ; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VC]]
+; CHECKM1: aese {{v[0-7].16b}}, {{v[0-7].16b}}
 ; CHECKM1: aese [[VD:v[0-7].16b]], {{v[0-7].16b}}
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Do you know why the generated code for exynos-m1  changed? Maybe it uses a different number of instructions to look ahead? I think we should be careful not to introduce any regressions before committing to this new approach.

I could run a few benchmarks on some Cortex-A cores to check for performance regressions, if you are happy with the state of the set of patches. 


https://reviews.llvm.org/D35260