[llvm] r308087 - [mips] Handle the `long-calls` feature flags in the MIPS backend
Simon Atanasyan via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 15 00:14:25 PDT 2017
Author: atanasyan
Date: Sat Jul 15 00:14:25 2017
New Revision: 308087
URL: http://llvm.org/viewvc/llvm-project?rev=308087&view=rev
Log:
[mips] Handle the `long-calls` feature flags in the MIPS backend
If the `long-calls` feature flags is enabled, disable use of the `jal`
instruction. Instead of that call a function by by first loading its
address into a register, and then using the contents of that register.
Differential revision: https://reviews.llvm.org/D35168
Added:
llvm/trunk/test/CodeGen/Mips/long-calls.ll
Modified:
llvm/trunk/lib/Target/Mips/Mips.td
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsSubtarget.h
Modified: llvm/trunk/lib/Target/Mips/Mips.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.td?rev=308087&r1=308086&r2=308087&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips.td Sat Jul 15 00:14:25 2017
@@ -190,6 +190,9 @@ def FeatureMadd4 : SubtargetFeature<"nom
def FeatureMT : SubtargetFeature<"mt", "HasMT", "true", "Mips MT ASE">;
+def FeatureLongCalls : SubtargetFeature<"long-calls", "UseLongCalls", "true",
+ "Disable use of the jal instruction">;
+
//===----------------------------------------------------------------------===//
// Mips processors supported.
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=308087&r1=308086&r2=308087&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Sat Jul 15 00:14:25 2017
@@ -3149,6 +3149,20 @@ MipsTargetLowering::LowerCall(TargetLowe
EVT Ty = Callee.getValueType();
bool GlobalOrExternal = false, IsCallReloc = false;
+ // The long-calls feature is ignored in case of PIC.
+ // While we do not support -mshared / -mno-shared properly,
+ // ignore long-calls in case of -mabicalls too.
+ if (Subtarget.useLongCalls() && !Subtarget.isABICalls() && !IsPIC) {
+ // Get the address of the callee into a register to prevent
+ // using of the `jal` instruction for the direct call.
+ if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee))
+ Callee = Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
+ : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
+ else if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee))
+ Callee = Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
+ : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
+ }
+
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
if (IsPIC) {
const GlobalValue *Val = G->getGlobal();
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=308087&r1=308086&r2=308087&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Sat Jul 15 00:14:25 2017
@@ -152,6 +152,9 @@ class MipsSubtarget : public MipsGenSubt
// HasMT -- support MT ASE.
bool HasMT;
+ // Disable use of the `jal` instruction.
+ bool UseLongCalls = false;
+
InstrItineraryData InstrItins;
// We can override the determination of whether we are in mips16 mode
@@ -269,6 +272,8 @@ public:
bool useSoftFloat() const { return IsSoftFloat; }
+ bool useLongCalls() const { return UseLongCalls; }
+
bool enableLongBranchPass() const {
return hasStandardEncoding() || allowMixed16_32();
}
Added: llvm/trunk/test/CodeGen/Mips/long-calls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/long-calls.ll?rev=308087&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/long-calls.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/long-calls.ll Sat Jul 15 00:14:25 2017
@@ -0,0 +1,57 @@
+; RUN: llc -march=mips -mattr=-long-calls %s -o - \
+; RUN: | FileCheck -check-prefix=OFF %s
+; RUN: llc -march=mips -mattr=+long-calls,+noabicalls %s -o - \
+; RUN: | FileCheck -check-prefix=ON32 %s
+
+; RUN: llc -march=mips -mattr=+long-calls,-noabicalls %s -o - \
+; RUN: | FileCheck -check-prefix=OFF %s
+
+; RUN: llc -march=mips64 -target-abi n32 -mattr=-long-calls %s -o - \
+; RUN: | FileCheck -check-prefix=OFF %s
+; RUN: llc -march=mips64 -target-abi n32 -mattr=+long-calls,+noabicalls %s -o - \
+; RUN: | FileCheck -check-prefix=ON32 %s
+
+; RUN: llc -march=mips64 -target-abi n64 -mattr=-long-calls %s -o - \
+; RUN: | FileCheck -check-prefix=OFF %s
+; RUN: llc -march=mips64 -target-abi n64 -mattr=+long-calls,+noabicalls %s -o - \
+; RUN: | FileCheck -check-prefix=ON64 %s
+
+declare void @callee()
+declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i32, i1)
+
+ at val = internal unnamed_addr global [20 x i32] zeroinitializer, align 4
+
+define void @caller() {
+
+; Use `jal` instruction with R_MIPS_26 relocation.
+; OFF: jal callee
+; OFF: jal memset
+
+; Save the `callee` and `memset` addresses in $25 register
+; and use `jalr` for the jumps.
+; ON32: lui $1, %hi(callee)
+; ON32: addiu $25, $1, %lo(callee)
+; ON32: jalr $25
+
+; ON32: addiu $1, $zero, %lo(memset)
+; ON32: lui $2, %hi(memset)
+; ON32: addu $25, $2, $1
+; ON32: jalr $25
+
+; ON64: lui $1, %highest(callee)
+; ON64: daddiu $1, $1, %higher(callee)
+; ON64: daddiu $1, $1, %hi(callee)
+; ON64: daddiu $25, $1, %lo(callee)
+; ON64: jalr $25
+
+; ON64: daddiu $1, $zero, %higher(memset)
+; ON64: lui $2, %highest(memset)
+; ON64: lui $2, %hi(memset)
+; ON64: daddiu $2, $zero, %lo(memset)
+; ON64: daddu $25, $1, $2
+; ON64: jalr $25
+
+ call void @callee()
+ call void @llvm.memset.p0i8.i32(i8* bitcast ([20 x i32]* @val to i8*), i8 0, i32 80, i32 4, i1 false)
+ ret void
+}
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