[PATCH] D34999: [AArch64] Avoid selecting XZR inline ASM memory operand

[Yi Kong via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL308060: [AArch64] Avoid selecting XZR inline ASM memory operand (authored by kongyi).

Changed prior to commit:
  https://reviews.llvm.org/D34999?vs=106704&id=106712#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D34999

Files:
  llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.cpp
  llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm.ll


Index: llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -167,7 +167,7 @@
 const TargetRegisterClass *
 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
                                       unsigned Kind) const {
-  return &AArch64::GPR64RegClass;
+  return &AArch64::GPR64spRegClass;
 }
 
 const TargetRegisterClass *
Index: llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -239,10 +239,17 @@
   case InlineAsm::Constraint_i:
   case InlineAsm::Constraint_m:
   case InlineAsm::Constraint_Q:
-    // Require the address to be in a register.  That is safe for all AArch64
-    // variants and it is hard to do anything much smarter without knowing
-    // how the operand is used.
-    OutOps.push_back(Op);
+    // We need to make sure that this one operand does not end up in XZR, thus
+    // require the address to be in a PointerRegClass register.
+    const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
+    const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF);
+    SDLoc dl(Op);
+    SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i64);
+    SDValue NewOp =
+        SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
+                                       dl, Op.getValueType(),
+                                       Op, RC), 0);
+    OutOps.push_back(NewOp);
     return false;
   }
   return true;
Index: llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm.ll
===================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm.ll
+++ llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm.ll
@@ -261,3 +261,13 @@
   ; CHECK: prfm pldl1keep, [x0]
   ret void
 }
+
+; PR33134
+define void @test_zero_address() {
+entry:
+; CHECK-LABEL: test_zero_address
+; CHECK: mov {{x[0-9]+}}, xzr
+; CHECK: ldr {{x[0-9]+}}, {{[x[0-9]+]}}
+  tail call i32 asm sideeffect "ldr $0, $1 \0A", "=r,*Q"(i32* null)
+  ret void
+}


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