[llvm] r308042 - [TableGen][MC] Fix a few places where we didn't hide the underlying type of LaneBitmask very well.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 14 11:30:09 PDT 2017
Author: ctopper
Date: Fri Jul 14 11:30:09 2017
New Revision: 308042
URL: http://llvm.org/viewvc/llvm-project?rev=308042&view=rev
Log:
[TableGen][MC] Fix a few places where we didn't hide the underlying type of LaneBitmask very well.
One place compared with 32, which I've replaced with LaneBitmask::BitWidth.
The other places are shifts of a constant 1 by a lane number. But if LaneBitmask were to be a larger type than 32-bits like 64-bits, the 1 would need to be 1ULL to do a 64-bit shift. To hide this I've added a LanebitMask::getLane that hides the shift and make sures the 1 is casted to correct type first.
Modified:
llvm/trunk/include/llvm/MC/LaneBitmask.h
llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
Modified: llvm/trunk/include/llvm/MC/LaneBitmask.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/LaneBitmask.h?rev=308042&r1=308041&r2=308042&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/LaneBitmask.h (original)
+++ llvm/trunk/include/llvm/MC/LaneBitmask.h Fri Jul 14 11:30:09 2017
@@ -75,6 +75,9 @@ namespace llvm {
static LaneBitmask getNone() { return LaneBitmask(0); }
static LaneBitmask getAll() { return ~LaneBitmask(0); }
+ static LaneBitmask getLane(unsigned Lane) {
+ return LaneBitmask(Type(1) << Lane);
+ }
private:
Type Mask = 0;
Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.cpp?rev=308042&r1=308041&r2=308042&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenRegisters.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenRegisters.cpp Fri Jul 14 11:30:09 2017
@@ -1268,12 +1268,12 @@ void CodeGenRegBank::computeSubRegLaneMa
CoveringLanes = LaneBitmask::getAll();
for (auto &Idx : SubRegIndices) {
if (Idx.getComposites().empty()) {
- if (Bit > 32) {
+ if (Bit > LaneBitmask::BitWidth) {
PrintFatalError(
Twine("Ran out of lanemask bits to represent subregister ")
+ Idx.getName());
}
- Idx.LaneMask = LaneBitmask(1 << Bit);
+ Idx.LaneMask = LaneBitmask::getLane(Bit);
++Bit;
} else {
Idx.LaneMask = LaneBitmask::getNone();
@@ -1298,9 +1298,9 @@ void CodeGenRegBank::computeSubRegLaneMa
static_assert(sizeof(Idx.LaneMask.getAsInteger()) == 4,
"Change Log2_32 to a proper one");
unsigned DstBit = Log2_32(Idx.LaneMask.getAsInteger());
- assert(Idx.LaneMask == LaneBitmask(1 << DstBit) &&
+ assert(Idx.LaneMask == LaneBitmask::getLane(DstBit) &&
"Must be a leaf subregister");
- MaskRolPair MaskRol = { LaneBitmask(1), (uint8_t)DstBit };
+ MaskRolPair MaskRol = { LaneBitmask::getLane(0), (uint8_t)DstBit };
LaneTransforms.push_back(MaskRol);
} else {
// Go through all leaf subregisters and find the ones that compose with
@@ -1314,7 +1314,7 @@ void CodeGenRegBank::computeSubRegLaneMa
continue;
// Replicate the behaviour from the lane mask generation loop above.
unsigned SrcBit = NextBit;
- LaneBitmask SrcMask = LaneBitmask(1 << SrcBit);
+ LaneBitmask SrcMask = LaneBitmask::getLane(SrcBit);
if (NextBit < LaneBitmask::BitWidth-1)
++NextBit;
assert(Idx2.LaneMask == SrcMask);
@@ -1386,7 +1386,7 @@ void CodeGenRegBank::computeSubRegLaneMa
// For classes without any subregisters set LaneMask to 1 instead of 0.
// This makes it easier for client code to handle classes uniformly.
if (LaneMask.none())
- LaneMask = LaneBitmask(1);
+ LaneMask = LaneBitmask::getLane(0);
RegClass.LaneMask = LaneMask;
}
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