[PATCH] D35307: [AArch64] Initial SVE register definitions

[Tim Northover via Phabricator via llvm-commits]

t.p.northover added inline comments.


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Comment at: lib/Target/AArch64/AArch64RegisterInfo.td:134
+
+// Purely virtual Vector Granule (VG) Dwarf register
+def VG : AArch64Reg<0, "vg">, DwarfRegNum<[46]>;
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sdesmalen wrote:
> rengolin wrote:
> > What's this? The "register" that stores the current length of the vectors?
> The VG Dwarf register indeed contains the length of an SVE vector, defined as the number of 64bit 'granules' in a vector (e.g. 2 for a 16byte vector). It is described in more detail here:
> https://developer.arm.com/docs/100985/0000
Does LLVM need to represent this (maybe for lldb??)? I could see it being plumbed through Uses/Defs like NZCV, but that seems a bit pointless since from what I've heard it's going to be essentially per-process (or near enough).


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Comment at: utils/TableGen/CodeGenDAGPatterns.cpp:546
     TypeSet InputSet(VTOperand);
-
-    auto I = remove_if(VTOperand.TypeVec, [NumElems](MVT VVT) {
-      return VVT.getVectorNumElements() >= NumElems;
+    // Logically a <2 x i32> should be a valid subvector of <n x 4 x i32>
+    // (so IsScalable && !OVT.isScalableIntegerVector() would be allowed)
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This is out of date if you're adopting Chris's `<scalable 4 x i32>` suggestion (which I also quite like).


Repository:
  rL LLVM

https://reviews.llvm.org/D35307