[PATCH] D35299: [AArch64] Tie source and destination operands for AESMC/AESIMC.

[Florian Hahn via Phabricator via llvm-commits]

fhahn updated this revision to Diff 106612.
fhahn edited the summary of this revision.
fhahn added a comment.

I've introduced AES(I)MCTrr pseudo instructions which have the "src = dst" constraint and patterns to use them for AES instruction pairs, if the result of the AESE/D in the pair has a single user.

I think this change keeps the codegen impact on CPUs that do not require the constraint to fuse AES instructions as small as possible, as the constraint should reduce register pressure and I don't expect AESMC instructions with the same source/destination register to be slower than if the registers are different.

@evandro does this address your concern? In my opinion adding a separate attribute seems not worth it.


https://reviews.llvm.org/D35299

Files:
  lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
  lib/Target/AArch64/AArch64InstrInfo.td
  lib/Target/AArch64/AArch64MacroFusion.cpp
  test/CodeGen/AArch64/misched-fusion-aes.ll

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