[llvm] r307904 - [ARM] GlobalISel: Support G_BR
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 13 04:09:34 PDT 2017
Author: rovka
Date: Thu Jul 13 04:09:34 2017
New Revision: 307904
URL: http://llvm.org/viewvc/llvm-project?rev=307904&view=rev
Log:
[ARM] GlobalISel: Support G_BR
This boils down to not crashing in reg bank select due to the lack of
register operands on this instruction, and adding some tests. The
instruction selection is already covered by the TableGen'erated code.
Modified:
llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=307904&r1=307903&r2=307904&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Thu Jul 13 04:09:34 2017
@@ -331,6 +331,9 @@ ARMRegisterBankInfo::getInstrMapping(con
&ARM::ValueMappings[ARM::DPR3OpsIdx]});
break;
}
+ case G_BR:
+ OperandsMapping = getOperandsMapping({nullptr});
+ break;
default:
return getInvalidInstructionMapping();
}
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir?rev=307904&r1=307903&r2=307904&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir Thu Jul 13 04:09:34 2017
@@ -45,6 +45,8 @@
define void @test_select_s32() { ret void }
define void @test_select_ptr() { ret void }
+ define void @test_br() { ret void }
+
define void @test_soft_fp_double() #0 { ret void }
attributes #0 = { "target-features"="+vfp2,-neonfp" }
@@ -1173,6 +1175,25 @@ body: |
; CHECK: BX_RET 14, _, implicit %r0
...
---
+name: test_br
+# CHECK-LABEL: name: test_br
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+body: |
+ ; CHECK: bb.0
+ bb.0:
+ successors: %bb.1(0x80000000)
+
+ ; CHECK: bb.1
+ bb.1:
+ successors: %bb.1(0x80000000)
+
+ ; CHECK: B %bb.1
+ G_BR %bb.1
+...
+---
name: test_soft_fp_double
# CHECK-LABEL: name: test_soft_fp_double
legalized: true
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll?rev=307904&r1=307903&r2=307904&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll Thu Jul 13 04:09:34 2017
@@ -420,3 +420,14 @@ entry:
%r = select i1 %cond, i32* %a, i32* %b
ret i32* %r
}
+
+define arm_aapcscc void @test_br() {
+; CHECK-LABEL: test_br
+; CHECK: [[LABEL:.L[[:alnum:]_]+]]:
+; CHECK: b [[LABEL]]
+entry:
+ br label %infinite
+
+infinite:
+ br label %infinite
+}
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=307904&r1=307903&r2=307904&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Thu Jul 13 04:09:34 2017
@@ -40,6 +40,8 @@
define void @test_select_s32() { ret void }
+ define void @test_br() { ret void }
+
define void @test_fadd_s32() #0 { ret void }
define void @test_fadd_s64() #0 { ret void }
@@ -830,6 +832,24 @@ body: |
...
---
+name: test_br
+# CHECK-LABEL: name: test_br
+legalized: true
+regBankSelected: false
+# CHECK: regBankSelected: true
+# There aren't any registers to map, but make sure we don't crash.
+selected: false
+body: |
+ bb.0:
+ successors: %bb.1(0x80000000)
+
+ bb.1:
+ successors: %bb.1(0x80000000)
+
+ G_BR %bb.1
+
+...
+---
name: test_fadd_s32
# CHECK-LABEL: name: test_fadd_s32
legalized: true
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