[PATCH] D35307: [AArch64] Initial SVE register definitions

[Will Lovett via Phabricator via llvm-commits]

willlovett added inline comments.


================
Comment at: lib/Target/AArch64/AArch64RegisterInfo.td:766
+}
+/*
+// SVE restricted 4 bit scalable vector register class
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fhahn wrote:
> Is the comment here intentional?
Yes.  Some encodings (eg. single precision FCMLA) restrict the addressable register set (in this case, the second input register) to Z0-15.  Similarly the 3-bit version below for half-precision restricts it to Z0-7


Repository:
  rL LLVM

https://reviews.llvm.org/D35307