[PATCH] D35307: [AArch64] Initial SVE register definitions

[Florian Hahn via Phabricator via llvm-commits]

fhahn added inline comments.


================
Comment at: lib/Target/AArch64/AArch64RegisterInfo.td:766
+}
+/*
+// SVE restricted 4 bit scalable vector register class
----------------
Is the comment here intentional?


Repository:
  rL LLVM

https://reviews.llvm.org/D35307