[llvm] r307779 - [mips][mt] Add missing files from last commit
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 12 05:33:40 PDT 2017
Author: sdardis
Date: Wed Jul 12 05:33:40 2017
New Revision: 307779
URL: http://llvm.org/viewvc/llvm-project?rev=307779&view=rev
Log:
[mips][mt] Add missing files from last commit
Added:
llvm/trunk/lib/Target/Mips/MipsMTInstrFormats.td
llvm/trunk/lib/Target/Mips/MipsMTInstrInfo.td
llvm/trunk/test/MC/Disassembler/Mips/mt/
llvm/trunk/test/MC/Disassembler/Mips/mt/valid-r2-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mt/valid-r2.txt
llvm/trunk/test/MC/Mips/mt/invalid.s
llvm/trunk/test/MC/Mips/mt/valid.s
Added: llvm/trunk/lib/Target/Mips/MipsMTInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMTInstrFormats.td?rev=307779&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMTInstrFormats.td (added)
+++ llvm/trunk/lib/Target/Mips/MipsMTInstrFormats.td Wed Jul 12 05:33:40 2017
@@ -0,0 +1,50 @@
+//===-- MipsMTInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Describe the MIPS MT instructions format
+//
+// opcode - operation code.
+// rt - destination register
+//
+//===----------------------------------------------------------------------===//
+
+class MipsMTInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
+ PredicateControl {
+ let DecoderNamespace = "Mips";
+ let EncodingPredicates = [HasStdEnc];
+}
+
+class OPCODE1<bits<1> Val> {
+ bits<1> Value = Val;
+}
+
+def OPCODE_SC_DMT : OPCODE1<0b0>;
+def OPCODE_SC_EMT : OPCODE1<0b1>;
+
+class FIELD5<bits<5> Val> {
+ bits<5> Value = Val;
+}
+
+def FIELD5_1_DMT_EMT : FIELD5<0b00001>;
+def FIELD5_2_DMT_EMT : FIELD5<0b01111>;
+
+class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
+ bits<32> Inst;
+
+ bits<5> rt;
+ let Inst{31-26} = 0b010000; // COP0
+ let Inst{25-21} = 0b01011; // MFMC0
+ let Inst{20-16} = rt;
+ let Inst{15-11} = Op1.Value;
+ let Inst{10-6} = Op2.Value;
+ let Inst{5} = sc.Value;
+ let Inst{4-3} = 0b00;
+ let Inst{2-0} = 0b001;
+}
Added: llvm/trunk/lib/Target/Mips/MipsMTInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMTInstrInfo.td?rev=307779&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMTInstrInfo.td (added)
+++ llvm/trunk/lib/Target/Mips/MipsMTInstrInfo.td Wed Jul 12 05:33:40 2017
@@ -0,0 +1,54 @@
+//===-- MipsMTInstrInfo.td - Mips MT Instruction Infos -----*- tablegen -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// MIPS MT Instruction Encodings
+//===----------------------------------------------------------------------===//
+
+class DMT_ENC : COP0_MFMC0_MT<FIELD5_1_DMT_EMT, FIELD5_2_DMT_EMT,
+ OPCODE_SC_DMT>;
+
+class EMT_ENC : COP0_MFMC0_MT<FIELD5_1_DMT_EMT, FIELD5_2_DMT_EMT,
+ OPCODE_SC_EMT>;
+
+//===----------------------------------------------------------------------===//
+// MIPS MT Instruction Descriptions
+//===----------------------------------------------------------------------===//
+
+class MT_1R_DESC_BASE<string instr_asm, InstrItinClass Itin = NoItinerary> {
+ dag OutOperandList = (outs GPR32Opnd:$rt);
+ dag InOperandList = (ins);
+ string AsmString = !strconcat(instr_asm, "\t$rt");
+ list<dag> Pattern = [];
+ InstrItinClass Itinerary = Itin;
+}
+
+class DMT_DESC : MT_1R_DESC_BASE<"dmt", II_DMT>;
+
+class EMT_DESC : MT_1R_DESC_BASE<"emt", II_EMT>;
+
+//===----------------------------------------------------------------------===//
+// MIPS MT Instruction Definitions
+//===----------------------------------------------------------------------===//
+let hasSideEffects = 1, isNotDuplicable = 1,
+ AdditionalPredicates = [NotInMicroMips] in {
+ def DMT : DMT_ENC, DMT_DESC, ASE_MT;
+
+ def EMT : EMT_ENC, EMT_DESC, ASE_MT;
+}
+
+//===----------------------------------------------------------------------===//
+// MIPS MT Instruction Definitions
+//===----------------------------------------------------------------------===//
+
+let AdditionalPredicates = [NotInMicroMips] in {
+ def : MipsInstAlias<"dmt", (DMT ZERO), 1>, ASE_MT;
+
+ def : MipsInstAlias<"emt", (EMT ZERO), 1>, ASE_MT;
+}
Added: llvm/trunk/test/MC/Disassembler/Mips/mt/valid-r2-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mt/valid-r2-el.txt?rev=307779&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mt/valid-r2-el.txt (added)
+++ llvm/trunk/test/MC/Disassembler/Mips/mt/valid-r2-el.txt Wed Jul 12 05:33:40 2017
@@ -0,0 +1,6 @@
+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=+mt | FileCheck %s
+0xc1 0x0b 0x60 0x41 # CHECK: dmt
+0xc1 0x0b 0x65 0x41 # CHECK: dmt $5
+0xe1 0x0b 0x60 0x41 # CHECK: emt
+0xe1 0x0b 0x64 0x41 # CHECK: emt $4
+
Added: llvm/trunk/test/MC/Disassembler/Mips/mt/valid-r2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mt/valid-r2.txt?rev=307779&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mt/valid-r2.txt (added)
+++ llvm/trunk/test/MC/Disassembler/Mips/mt/valid-r2.txt Wed Jul 12 05:33:40 2017
@@ -0,0 +1,6 @@
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+mt | FileCheck %s
+0x41 0x60 0x0b 0xc1 # CHECK: dmt
+0x41 0x65 0x0b 0xc1 # CHECK: dmt $5
+0x41 0x60 0x0b 0xe1 # CHECK: emt
+0x41 0x64 0x0b 0xe1 # CHECK: emt $4
+
Added: llvm/trunk/test/MC/Mips/mt/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mt/invalid.s?rev=307779&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mt/invalid.s (added)
+++ llvm/trunk/test/MC/Mips/mt/invalid.s Wed Jul 12 05:33:40 2017
@@ -0,0 +1,7 @@
+# RUN: not llvm-mc -arch=mips -mcpu=mips32 -mattr=+mt < %s 2>&1 | FileCheck %s
+ dmt 4 # CHECK: error: invalid operand for instruction
+ dmt $4, $5 # CHECK: error: invalid operand for instruction
+ dmt $5, 0($4) # CHECK: error: invalid operand for instruction
+ emt 4 # CHECK: error: invalid operand for instruction
+ emt $4, $5 # CHECK: error: invalid operand for instruction
+ emt $5, 0($5) # CHECK: error: invalid operand for instruction
Added: llvm/trunk/test/MC/Mips/mt/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mt/valid.s?rev=307779&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mt/valid.s (added)
+++ llvm/trunk/test/MC/Mips/mt/valid.s Wed Jul 12 05:33:40 2017
@@ -0,0 +1,6 @@
+# RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s \
+# RUN: | FileCheck %s
+ dmt # CHECK: dmt # encoding: [0x41,0x60,0x0b,0xc1]
+ dmt $5 # CHECK: dmt $5 # encoding: [0x41,0x65,0x0b,0xc1]
+ emt # CHECK: emt # encoding: [0x41,0x60,0x0b,0xe1]
+ emt $4 # CHECK: emt $4 # encoding: [0x41,0x64,0x0b,0xe1]
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