[PATCH] D35299: [AArch64] Tie source and destination operands for AESMC/AESIMC.
Florian Hahn via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 12 05:06:38 PDT 2017
fhahn created this revision.
Herald added subscribers: javed.absar, aemerson.
Most CPUs implementing AES fusion require instruction pairs of the form
AESE Vn, _
AESMC Vn, Vn
and
AESD Vn, _
AESIMC Vn, Vn
The new constraint in AArch64InstrFormats.td
makes sure source and destination registers for AESMC/AESIMC are the same.
Dependent on how the register allocator happens to be assigning
registers before this patch, this patch can give a large speedup on
benchmarks benefiting from AES fusion.
As it is, this constraint applies to all AESMC/AESIMC instructions. If
that's a concern, I think there would be 2 ways to limit the scope of
the constraint:
(1) Add pseudo instructions for AESMC/AESIMC. When expanding them, tie
the src and dst operands, if the subtarget has FeatureFuseAES.
Maybe there is an easier way to only have the constraint for
subtargets that have FeatureFuseAES.
(2) Substitute virtual registers during macro fusion. The major problem
when doing it there, I think, is that it is too late to use
MachineInstr::tieOperands, as virtual registers have been assigned
already. We could substitute the destination register with the
source register and update all uses of the destination register. I
am not sure what the best way to update the register live ranges
used by the MachineScheduler would be, though.
A nice side effect of this change is that now all possible pairs are
scheduled back-to-back on the exynos-m1 for the misched-fusion-aes.ll
test case.
I had to update aes_load_store. The version I added initially was very
reduced and with the new constraint, AESE/AESMC could not be scheduled
back-to-back. I updated the test to be more realistic and still expose
the same scheduling problem as the initial test case.
https://reviews.llvm.org/D35299
Files:
lib/Target/AArch64/AArch64InstrFormats.td
test/CodeGen/AArch64/misched-fusion-aes.ll
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