[llvm] r307679 - [mips][mt][1/7] Add the MT ASE as a subtarget feature.

[Simon Dardis via llvm-commits]

Author: sdardis
Date: Tue Jul 11 11:03:20 2017
New Revision: 307679

URL: http://llvm.org/viewvc/llvm-project?rev=307679&view=rev
Log:
[mips][mt][1/7] Add the MT ASE as a subtarget feature.

Preparatory work for adding the MIPS MT (multi-threading) ASE instructions.

Reviewers: slthakur, atanasyan

Differential Revision: https://reviews.llvm.org/D35247

Added:
    llvm/trunk/test/MC/Mips/mt/
    llvm/trunk/test/MC/Mips/mt/abiflag.s
Modified:
    llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
    llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h
    llvm/trunk/lib/Target/Mips/Mips.td
    llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
    llvm/trunk/lib/Target/Mips/MipsSubtarget.h

Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=307679&r1=307678&r2=307679&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Tue Jul 11 11:03:20 2017
@@ -628,6 +628,9 @@ public:
   bool useSoftFloat() const {
     return getSTI().getFeatureBits()[Mips::FeatureSoftFloat];
   }
+  bool hasMT() const {
+    return getSTI().getFeatureBits()[Mips::FeatureMT];
+  }
 
   /// Warn if RegIndex is the same as the current AT.
   void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc);

Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h?rev=307679&r1=307678&r2=307679&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h Tue Jul 11 11:03:20 2017
@@ -159,6 +159,8 @@ public:
       ASESet |= Mips::AFL_ASE_MICROMIPS;
     if (P.inMips16Mode())
       ASESet |= Mips::AFL_ASE_MIPS16;
+    if (P.hasMT())
+      ASESet |= Mips::AFL_ASE_MT;
   }
 
   template <class PredicateLibrary>

Modified: llvm/trunk/lib/Target/Mips/Mips.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.td?rev=307679&r1=307678&r2=307679&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips.td Tue Jul 11 11:03:20 2017
@@ -188,6 +188,8 @@ def FeatureUseTCCInDIV : SubtargetFeatur
 def FeatureMadd4 : SubtargetFeature<"nomadd4", "DisableMadd4", "true",
                                     "Disable 4-operand madd.fmt and related instructions">;
 
+def FeatureMT : SubtargetFeature<"mt", "HasMT", "true", "Mips MT ASE">;
+
 //===----------------------------------------------------------------------===//
 // Mips processors supported.
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=307679&r1=307678&r2=307679&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Tue Jul 11 11:03:20 2017
@@ -70,7 +70,8 @@ MipsSubtarget::MipsSubtarget(const Tripl
       InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
       HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
       Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
-      HasEVA(false), DisableMadd4(false), TM(TM), TargetTriple(TT), TSInfo(),
+      HasEVA(false), DisableMadd4(false), HasMT(false), TM(TM),
+      TargetTriple(TT), TSInfo(),
       InstrInfo(
           MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
       FrameLowering(MipsFrameLowering::create(*this)),

Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=307679&r1=307678&r2=307679&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Tue Jul 11 11:03:20 2017
@@ -149,6 +149,9 @@ class MipsSubtarget : public MipsGenSubt
   // related instructions.
   bool DisableMadd4;
 
+  // HasMT -- support MT ASE.
+  bool HasMT;
+
   InstrItineraryData InstrItins;
 
   // We can override the determination of whether we are in mips16 mode
@@ -259,6 +262,7 @@ public:
   bool hasMSA() const { return HasMSA; }
   bool disableMadd4() const { return DisableMadd4; }
   bool hasEVA() const { return HasEVA; }
+  bool hasMT() const { return HasMT; }
   bool useSmallSection() const { return UseSmallSection; }
 
   bool hasStandardEncoding() const { return !inMips16Mode(); }

Added: llvm/trunk/test/MC/Mips/mt/abiflag.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mt/abiflag.s?rev=307679&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mt/abiflag.s (added)
+++ llvm/trunk/test/MC/Mips/mt/abiflag.s Tue Jul 11 11:03:20 2017
@@ -0,0 +1,10 @@
+# RUN: llvm-mc < %s -arch=mips -mcpu=mips32r2 -mattr=+mt -filetype=obj -o - \
+# RUN:   | llvm-readobj -mips-abi-flags | FileCheck %s
+
+# Test that the usage of the MT ASE is recorded in .MIPS.abiflags
+
+# CHECK: ASEs
+# CHECK-NEXT: MT (0x40)
+
+ .text
+  nop