[PATCH] D35007: [PowerPC] Do not emit displacements for DQ-Form instructions that aren't multiples of 16

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added a comment.

In https://reviews.llvm.org/D35007#805153, @hfinkel wrote:

> > Although the instruction doesn't require any special alignment, allowing it to be used with weaker alignment allows other passes to modify the offset after ISEL.
>
> For what other passes is this true (aside from places dealing with frame indices, which it seems like you're fixing regardless)?


I actually don't know that. I thought I had seen that before I fixed all the FrameIndex stuff, but looking back on it - it was also FI related. Do you think I should go back to the original way of testing for the displacement operand, but keep the FI fixes?



================
Comment at: lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp:274
   const MCOperand &MO = MI.getOperand(OpNo);
-  assert(MO.isImm());
+  assert(MO.isImm() && !(MO.getImm() % 16) &&
+         "Expecting an immediate that is a multiple of 16");
----------------
hfinkel wrote:
> If you use the builtin assembler directly, can a user hit this assert? If so, we should put an actual diagnostic somewhere.
No, the internal assembler already handles the diagnostic due to the definition of the instruction due to the definition of the operand being correct:
`isS16ImmX16` is already defined to test for whether the operand is a multiple of 16.


Repository:
  rL LLVM

https://reviews.llvm.org/D35007