[llvm] r307659 - [globalisel][tablegen] Change method of squashing unused variable warnings following post-commit comments.

Daniel Sanders via llvm-commits llvm-commits at lists.llvm.org
Tue Jul 11 07:23:14 PDT 2017


Author: dsanders
Date: Tue Jul 11 07:23:14 2017
New Revision: 307659

URL: http://llvm.org/viewvc/llvm-project?rev=307659&view=rev
Log:
[globalisel][tablegen] Change method of squashing unused variable warnings following post-commit comments.


Modified:
    llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h

Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h?rev=307659&r1=307658&r2=307659&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h Tue Jul 11 07:23:14 2017
@@ -30,13 +30,14 @@ bool InstructionSelector::executeMatchTa
   while (true) {
     switch (*Command++) {
     case GIM_RecordInsn: {
-      int64_t NewInsnID LLVM_ATTRIBUTE_UNUSED = *Command++;
+      int64_t NewInsnID = *Command++;
       int64_t InsnID = *Command++;
       int64_t OpIdx = *Command++;
 
       // As an optimisation we require that MIs[0] is always the root. Refuse
       // any attempt to modify it.
       assert(NewInsnID != 0 && "Refusing to modify MIs[0]");
+      (void)NewInsnID;
 
       MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
       if (!MO.isReg()) {
@@ -203,10 +204,11 @@ bool InstructionSelector::executeMatchTa
       break;
     }
     case GIR_BuildMI: {
-      int64_t InsnID LLVM_ATTRIBUTE_UNUSED = *Command++;
+      int64_t InsnID = *Command++;
       int64_t Opcode = *Command++;
       assert((size_t)InsnID == OutMIs.size() &&
              "Expected to store MIs in order");
+      (void)InsnID;
       OutMIs.push_back(BuildMI(*State.MIs[0]->getParent(), State.MIs[0],
                                State.MIs[0]->getDebugLoc(), TII.get(Opcode)));
       DEBUG(dbgs() << "GIR_BuildMI(OutMIs[" << InsnID << "], " << Opcode




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