[PATCH] D35228: [TableGen] Add support for instruction clusters

[Javed Absar via Phabricator via llvm-commits]

javed.absar added inline comments.


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Comment at: llvm/include/llvm/MC/MCSchedule.h:93
 
   bool operator==(const MCReadAdvanceEntry &Other) const {
     return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
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Shouldn't this function be amended as well to equate Cluster?


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Comment at: llvm/include/llvm/Target/TargetSchedule.td:312
 // SchedModel ties these resources to a processor.
-class ProcReadAdvance<int cycles, list<SchedWrite> writes = []> {
+class ProcReadAdvance<int cycles, list<SchedWrite> writes = [], bit cluster> {
   int Cycles = cycles;
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Perhaps the order of the parameters should be - cycles, cluster, writes = [] 


Repository:
  rL LLVM

https://reviews.llvm.org/D35228