[llvm] r307630 - [GlobalISel][X86] Use correct AND instructions.
Igor Breger via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 11 01:04:51 PDT 2017
Author: ibreger
Date: Tue Jul 11 01:04:51 2017
New Revision: 307630
URL: http://llvm.org/viewvc/llvm-project?rev=307630&view=rev
Log:
[GlobalISel][X86] Use correct AND instructions.
AND8ri8 not supported in 64bit.
Modified:
llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext.mir
Modified: llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp?rev=307630&r1=307629&r2=307630&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp Tue Jul 11 01:04:51 2017
@@ -642,7 +642,7 @@ bool X86InstructionSelector::selectZext(
unsigned AndOpc;
if (DstTy == LLT::scalar(8))
- AndOpc = X86::AND8ri8;
+ AndOpc = X86::AND8ri;
else if (DstTy == LLT::scalar(16))
AndOpc = X86::AND16ri8;
else if (DstTy == LLT::scalar(32))
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext.mir?rev=307630&r1=307629&r2=307630&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext.mir Tue Jul 11 01:04:51 2017
@@ -51,7 +51,7 @@ registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
# ALL: %0 = COPY %dil
-# ALL-NEXT: %1 = AND8ri8 %0, 1, implicit-def %eflags
+# ALL-NEXT: %1 = AND8ri %0, 1, implicit-def %eflags
# ALL-NEXT: %al = COPY %1
# ALL-NEXT: RET 0, implicit %al
body: |
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