[llvm] r307624 - [PowerPC] fix latency for simple integer instructions in POWER9 scheduler

Hiroshi Inoue via llvm-commits llvm-commits at lists.llvm.org
Mon Jul 10 22:37:16 PDT 2017


Author: inouehrs
Date: Mon Jul 10 22:37:16 2017
New Revision: 307624

URL: http://llvm.org/viewvc/llvm-project?rev=307624&view=rev
Log:
[PowerPC] fix latency for simple integer instructions in POWER9 scheduler

In the POWER9 instruction scheduler, SchedWriteRes for the simple integer instructions are misconfigured to use that of (costly) DFU instructions.
This results in surprisingly long instruction latency estimation and causes misbehavior in some optimizers such as if-conversion.

Differential Revision: https://reviews.llvm.org/D34869


Modified:
    llvm/trunk/lib/Target/PowerPC/PPCScheduleP9.td

Modified: llvm/trunk/lib/Target/PowerPC/PPCScheduleP9.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleP9.td?rev=307624&r1=307623&r2=307624&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleP9.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleP9.td Mon Jul 10 22:37:16 2017
@@ -260,7 +260,7 @@ let SchedModel = P9Model in {
 
   // ***************** Defining Itinerary Class Resources *****************
 
-  def : ItinRW<[P9_DFU_76C, IP_EXEC_1C, DISP_1C, DISP_1C], [IIC_IntSimple,
+  def : ItinRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C], [IIC_IntSimple,
                                          IIC_IntGeneral]>;
 
   def : ItinRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],




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