[PATCH] D34986: [PowerPC] avoid redundant analysis while lowering an immediate; NFC

[Hiroshi Inoue via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL307623: [PowerPC] avoid redundant analysis while lowering an immediate; NFC (authored by inouehrs).

Changed prior to commit:
  https://reviews.llvm.org/D34986?vs=105178&id=105963#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D34986

Files:
  llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp


Index: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -709,7 +709,10 @@
 
 static unsigned getInt64Count(int64_t Imm) {
   unsigned Count = getInt64CountDirect(Imm);
-  if (Count == 1)
+
+  // If the instruction count is 1 or 2, we do not need further analysis
+  // since rotate + load constant requires at least 2 instructions.
+  if (Count <= 2)
     return Count;
 
   for (unsigned r = 1; r < 63; ++r) {
@@ -819,7 +822,10 @@
 
 static SDNode *getInt64(SelectionDAG *CurDAG, const SDLoc &dl, int64_t Imm) {
   unsigned Count = getInt64CountDirect(Imm);
-  if (Count == 1)
+
+  // If the instruction count is 1 or 2, we do not need further analysis
+  // since rotate + load constant requires at least 2 instructions.
+  if (Count <= 2)
     return getInt64Direct(CurDAG, dl, Imm);
 
   unsigned RMin = 0;


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D34986.105963.patch
Type: text/x-patch
Size: 991 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170711/6e1b3aa0/attachment.bin>