[llvm] r307622 - [AVR] Remove a few very old TODOs that don't have enough context to understand

[Dylan McKay via llvm-commits]

Author: dylanmckay
Date: Mon Jul 10 22:14:40 2017
New Revision: 307622

URL: http://llvm.org/viewvc/llvm-project?rev=307622&view=rev
Log:
[AVR] Remove a few very old TODOs that don't have enough context to understand

Modified:
    llvm/trunk/lib/Target/AVR/AVRAsmPrinter.cpp
    llvm/trunk/lib/Target/AVR/AVRRegisterInfo.td

Modified: llvm/trunk/lib/Target/AVR/AVRAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRAsmPrinter.cpp?rev=307622&r1=307621&r2=307622&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/AVR/AVRAsmPrinter.cpp Mon Jul 10 22:14:40 2017
@@ -149,7 +149,10 @@ bool AVRAsmPrinter::PrintAsmMemoryOperan
   (void)MO;
   assert(MO.isReg() && "Unexpected inline asm memory operand");
 
-  // TODO: We can look up the alternative name for the register if it's given.
+  // TODO: We should be able to look up the alternative name for
+  // the register if it's given.
+  // TableGen doesn't expose a way of getting retrieving names
+  // for registers.
   if (MI->getOperand(OpNum).getReg() == AVR::R31R30) {
     O << "Z";
   } else {

Modified: llvm/trunk/lib/Target/AVR/AVRRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRRegisterInfo.td?rev=307622&r1=307621&r2=307622&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/AVR/AVRRegisterInfo.td Mon Jul 10 22:14:40 2017
@@ -202,8 +202,6 @@ def ZREG : RegisterClass<"AVR", [i16], 8
 // Register class used for the stack read pseudo instruction.
 def GPRSP: RegisterClass<"AVR", [i16], 8, (add SP)>;
 
-//:TODO: if we remove this we get an error in tablegen
-//:TODO: this is just a hack, remove it once add16 works!
 // Status register.
 def SREG : AVRReg<14, "FLAGS">, DwarfRegNum<[88]>;
 def CCR : RegisterClass<"AVR", [i8], 8, (add SREG)>