[PATCH] D34854: Allow GHC calling convention to use YMM and ZMM registers

[Simon Pilgrim via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL307504: [X86] Allow GHC calling convention to use YMM and ZMM registers (authored by RKSimon).

Changed prior to commit:
  https://reviews.llvm.org/D34854?vs=104799&id=105783#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D34854

Files:
  llvm/trunk/lib/Target/X86/X86CallingConv.td


Index: llvm/trunk/lib/Target/X86/X86CallingConv.td
===================================================================
--- llvm/trunk/lib/Target/X86/X86CallingConv.td
+++ llvm/trunk/lib/Target/X86/X86CallingConv.td
@@ -651,7 +651,15 @@
   // Pass in STG registers: F1, F2, F3, F4, D1, D2
   CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
             CCIfSubtarget<"hasSSE1()",
-            CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
+            CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>,
+  // AVX
+  CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
+            CCIfSubtarget<"hasAVX()",
+            CCAssignToReg<[YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>>,
+  // AVX-512
+  CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
+            CCIfSubtarget<"hasAVX512()",
+            CCAssignToReg<[ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6]>>>
 ]>;
 
 def CC_X86_64_HiPE : CallingConv<[


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D34854.105783.patch
Type: text/x-patch
Size: 928 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170709/fa642525/attachment.bin>