[PATCH] D35007: [PowerPC] Do not emit displacements for DQ-Form instructions that aren't multiples of 16

[Tony Jiang via Phabricator via llvm-commits]

jtony added inline comments.


================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:2143
     if (isIntS16Immediate(N.getOperand(1), imm) &&
-        (!Aligned || (imm & 3) == 0)) {
+        (!Alignment || (imm % Alignment) == 0)) {
       Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
----------------
Minor nit, the variable "imm" should be Imm, we can fix it in this patch.


================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:2167
     if (isIntS16Immediate(N.getOperand(1), imm) &&
-        (!Aligned || (imm & 3) == 0)) {
+        (!Alignment || (imm % Alignment) == 0)) {
       // If this is an or of disjoint bitfields, we can codegen this as an add
----------------
Same here.


================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:2194
     short Imm;
-    if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
+    if (isIntS16Immediate(CN, Imm) && (!Alignment || (Imm % Alignment) == 0)) {
       Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
----------------
This one is already correct.


================
Comment at: lib/Target/PowerPC/PPCRegisterInfo.cpp:895
          "This should be handled in a target-independent way");
-  if (!noImmForm && ((isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) ||
+  if (!noImmForm && ((isInt<16>(Offset) &&
+                      ((Offset % offsetMinAlign(MI)) == 0)) ||
----------------
noImmForm  --> NoImmForm 


================
Comment at: test/CodeGen/PowerPC/PR33671.ll:1
+; Function Attrs: norecurse nounwind
+; RUN: llc -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 < %s | FileCheck %s
----------------
These Attrs are unnecessary, right?


Repository:
  rL LLVM

https://reviews.llvm.org/D35007