[PATCH] D34999: [CodeGen] InstrEmitter should constrain register class for inline ASM

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Is this really the best place to solve this issue?

PowerPC has a similar problem (r0 can't be used for memory addresses); the PPC backend solves it in PPCDAGToDAGISel::SelectInlineAsmMemoryOperand.

For non-memory inline asm operands, SelectionDAGBuilder::visitInlineAsm has code to constrain the register classes.



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Comment at: lib/CodeGen/SelectionDAG/InstrEmitter.cpp:161
+              }
             }
             if (!UseRC)
----------------
Let me see if I follow this correctly.  At this point, either isMachineOpcode is true, or the opcode is one of the ones listed in the switch in InstrEmitter::EmitSpecialNode (ISD::MERGE_VALUES, ISD::TokenFactor, ISD::CopyToReg, ISD::CopyFromReg, ISD::EH_LABEL, ISD::LIFETIME_START, ISD::LIFETIME_END, and ISD::INLINEASM).  For machine opcodes, we use getRegClass() to get the register class.  For inline asm, we use this new code (roughly equivalent to MachineInstr::getRegClassConstraint) to get the register class.  For the other opcodes, the register class doesn't matter...?

InstrEmitter::AddRegisterOperand has similar code to retrieve a regclass for an operand; do we also need to special-case inline asm there?


Repository:
  rL LLVM

https://reviews.llvm.org/D34999