[PATCH] D34961: [AArch64] Use 16 bytes as preferred function alignment on Cortex-A72.

[Kristof Beyls via Phabricator via llvm-commits]

kristof.beyls added a comment.

In https://reviews.llvm.org/D34961#800945, @mcrosier wrote:

> From a coding standpoint this all LGTM.  However, I'm going to defer to a A72 code owner for final approval.


LGTM from a Cortex-A72 point-of-view: this patch is generating code in line with the optimization guide recommendations and the benchmark numbers quoted look good.


https://reviews.llvm.org/D34961