[PATCH] D33099: AMD Jaguar scheduler doesn't correctly model 256-bit AVX instructions

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:417
+}
+def : InstRW<[WriteVMULYPS], (instregex "VMULPSYrr", "VRVPPSYr", "VRSQRTPSYr")>;
+
----------------
VRVPPSYr -> VRCPPSYr ?


================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:423
+}
+def : InstRW<[WriteVMULYPSLd, ReadAfterLd], (instregex "VMULPSYrm", "VRVPPSYm", "VRSQRTPSYm")>;
+
----------------
VRVPPSYm -> VRCPPSYm ?


================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:425
+
+def WriteVDPYPS: SchedWriteRes<[JFPU1, JFPU0]> {
+  let Latency = 12;
----------------
WriteVDPPSY


================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:431
+
+def WriteVDPYPSLd: SchedWriteRes<[JLAGU, JFPU1, JFPU0]> {
+  let Latency = 17;
----------------
WriteVDPPSYLd


================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:447
+}
+def : InstRW<[WriteVCVTLd, ReadAfterLd], (instregex "VCVTDQ2P(S|D)Yrm", "VROUNDYP(S|D)r")>;
+
----------------
VROUNDYP(S|D)rm ?


https://reviews.llvm.org/D33099