[llvm] r307245 - [ARM] GlobalISel: Map s32 G_FCMP in reg bank select

[Diana Picus via llvm-commits]

Author: rovka
Date: Thu Jul  6 02:57:46 2017
New Revision: 307245

URL: http://llvm.org/viewvc/llvm-project?rev=307245&view=rev
Log:
[ARM] GlobalISel: Map s32 G_FCMP in reg bank select

Map hard G_FCMP operands to FPR and the result to GPR.

Modified:
    llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
    llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=307245&r1=307244&r2=307245&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Thu Jul  6 02:57:46 2017
@@ -277,6 +277,20 @@ ARMRegisterBankInfo::getInstrMapping(con
                             &ARM::ValueMappings[ARM::GPR3OpsIdx]});
     break;
   }
+  case G_FCMP: {
+    LLT Ty1 = MRI.getType(MI.getOperand(2).getReg());
+    (void)Ty1;
+    LLT Ty2 = MRI.getType(MI.getOperand(3).getReg());
+    (void)Ty2;
+    assert(Ty.getSizeInBits() == 1 && "Unsupported size for G_FCMP");
+    assert(Ty1.getSizeInBits() == 32 && "Unsupported size for G_FCMP");
+    assert(Ty2.getSizeInBits() == 32 && "Unsupported size for G_FCMP");
+    OperandsMapping =
+        getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr,
+                            &ARM::ValueMappings[ARM::SPR3OpsIdx],
+                            &ARM::ValueMappings[ARM::SPR3OpsIdx]});
+    break;
+  }
   case G_MERGE_VALUES: {
     // We only support G_MERGE_VALUES for creating a double precision floating
     // point value out of two GPRs.

Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=307245&r1=307244&r2=307245&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Thu Jul  6 02:57:46 2017
@@ -35,6 +35,7 @@
   define void @test_trunc_s32_16() { ret void }
 
   define void @test_icmp_eq_s32() { ret void }
+  define void @test_fcmp_one_s32() #0 { ret void }
 
   define void @test_select_s32() { ret void }
 
@@ -740,6 +741,34 @@ body:             |
     %3(s32) = G_ZEXT %2(s1)
     %r0 = COPY %3(s32)
     BX_RET 14, _, implicit %r0
+
+...
+---
+name:            test_fcmp_one_s32
+# CHECK-LABEL: name: test_fcmp_one_s32
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: fprb, preferred-register: '' }
+# CHECK: - { id: 1, class: fprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
+
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+body:             |
+  bb.0:
+    liveins: %s0, %s1
+
+    %0(s32) = COPY %s0
+    %1(s32) = COPY %s1
+    %2(s1) = G_FCMP floatpred(one), %0(s32), %1
+    %3(s32) = G_ZEXT %2(s1)
+    %r0 = COPY %3(s32)
+    BX_RET 14, _, implicit %r0
 
 ...
 ---