[PATCH] D35014: [X86] PR32755 : Improvement in CodeGen instruction selection for LEAs.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: lib/Target/X86/X86ISelDAGToDAG.cpp:1418
+          AM.IndexReg = Base_Reg;
+          AM.Scale++;
+          return false;
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Is Scale limited to 1 before this or could it be 2 in which case this creates an illegal scale of 3?


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Comment at: lib/Target/X86/X86OptimizeLEAs.cpp:70
+           const MachineOperand *Disp, bool DispCheck = false)
+      : Disp(Disp),HardDispCheck(DispCheck) {
     Operands[0] = Base;
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Need a space before HardDispCheck.


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Comment at: lib/Target/X86/X86OptimizeLEAs.cpp:89
+      return isIdenticalOp(*Disp,*Other.Disp);
+    else
+      return isSimilarDispOp(*Disp, *Other.Disp);
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No need for 'else' after an if that returns.


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Comment at: lib/Target/X86/X86OptimizeLEAs.cpp:196
+                  &MI.getOperand(N + X86::AddrSegmentReg),
+                  &MI.getOperand(N + X86::AddrDisp),true);
+}
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Add space before 'true'


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Comment at: utils/TableGen/DAGISelMatcherGen.cpp:308
   // If this is an 'and R, 1234' where the operation is AND/OR and the RHS is
-  // a constant without a predicate fn that has more that one bit set, handle
+  // a constant without a predicate fn that has more than one bit set, handle
   // this as a special case.  This is usually for targets that have special
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This should be a NFC pre-commit.


https://reviews.llvm.org/D35014